3- Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Jinbong | - |
| dc.contributor.author | Lee, Kwyro | - |
| dc.date.accessioned | 2010-12-10T01:20:00Z | - |
| dc.date.available | 2010-12-10T01:20:00Z | - |
| dc.date.issued | 2003-12 | - |
| dc.identifier.citation | Journal of Semiconductor Technology and Science | en |
| dc.identifier.uri | http://hdl.handle.net/10203/20922 | - |
| dc.description.abstract | A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits. | en |
| dc.description.sponsorship | This work is supported by MICROS Research Center. The authors wish to thank Kwangmyoung.Rho at KAIST and Dr. Yougjin.Kim, Dr. Kyuhyoun.Kim, Dr. Kyungtae. Kim at Samsung Electronics Co. Ltd. for their advices and fruitful discussions. | en |
| dc.language.iso | en_US | en |
| dc.publisher | 대한전자공학회 | en |
| dc.subject | CMOS antifuse | en |
| dc.subject | OTP ROM | en |
| dc.subject | gateoxide breakdown | en |
| dc.title | 3- Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse | en |
| dc.type | Article | en |
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- EE-Journal Papers(저널논문)
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