DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Si-Nai | ko |
dc.contributor.author | Kim, Mee-Ran | ko |
dc.contributor.author | Sung, Ba-Ro-Saim | ko |
dc.contributor.author | Kang, Hyun-Wook | ko |
dc.contributor.author | Cho, Min-Hyung | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2016-06-07T08:57:05Z | - |
dc.date.available | 2016-06-07T08:57:05Z | - |
dc.date.created | 2016-02-25 | - |
dc.date.created | 2016-02-25 | - |
dc.date.issued | 2016-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.794 - 798 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/207643 | - |
dc.description.abstract | A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-frequency dynamic linearity. The proposed binary structure realizes a compact DAC by eliminating the need for additional circuits, such as thermometer decoders, and thus reduces power consumption. A prototype 6-bit 3.1-GS/s full-binary DAC was fabricated in a 90-nm CMOS process. The DAC exhibits a spurious-free dynamic range of >37.2 dB up to 3.1 GS/s over the Nyquist input. The chip consumes 17.7 mW of power and occupies 0.038 mm(2) of core size. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm(2) | - |
dc.type | Article | - |
dc.identifier.wosid | 000369479500037 | - |
dc.identifier.scopusid | 2-s2.0-84925858240 | - |
dc.type.rims | ART | - |
dc.citation.volume | 24 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 794 | - |
dc.citation.endingpage | 798 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2015.2412657 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Kim, Mee-Ran | - |
dc.contributor.nonIdAuthor | Cho, Min-Hyung | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Current steering | - |
dc.subject.keywordAuthor | digital-to-analog converter (DAC) | - |
dc.subject.keywordAuthor | full binary | - |
dc.subject.keywordAuthor | wideband dynamic linearity | - |
dc.subject.keywordPlus | GS/S DAC | - |
dc.subject.keywordPlus | CMOS | - |
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