The 3-D stacking technologies have been developed, because higher packaging density demands to populate more circuits or chips on smaller substrate areas. Among 3-D packaging technologies, the through silicon via (TSV) technology that uses Cu pillar/Sn-Ag microbumps to vertically interconnect between chips is the most advanced state-of-the-art packaging method. However, the conventional reflow process with flux and underfill for bonding using Cu pillar/Sn-Ag microbumps has problems, such as process complexity, flux residues entrapment, and voids trapping. In this paper, the B-stage nonconductive films (NCFs) have been introduced to simplify the bonding processes and avoid flux residues entrapment and voids trapping. In addition, wafer-level packages (WLPs) using NCFs for the 3-D-TSV microbump interconnection have also been investigated. At first, the wafer-level NCFs lamination was conducted without voids and bubbles formation on a wafer. And the effect of epoxy resin types on the adhesion and elongation properties of NCFs laminated on a wafer was also investigated to optimize the wafer dicing process using laminated NCFs. After NCF-laminated Cu/Sn-Ag bumped wafer was diced into a single chip, singulated chips were bonded on substrate chips using a flip chip bonder. The electrical properties and reliabilities of the WLP packages using NCFs were evaluated and compared with the conventional single flip chip packages. As a result, the WLPs using the B-stage NCFs showed the same electrical interconnection properties as those of the conventional single flip chip packages.