DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han K. | ko |
dc.contributor.author | Lee, Kwyro | ko |
dc.contributor.author | Shin H. | ko |
dc.date.accessioned | 2010-12-03T07:16:27Z | - |
dc.date.available | 2010-12-03T07:16:27Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2004-12 | - |
dc.identifier.citation | SOLID-STATE ELECTRONICS, v.48, no.12, pp.2255 - 2262 | - |
dc.identifier.issn | 0038-1101 | - |
dc.identifier.uri | http://hdl.handle.net/10203/20692 | - |
dc.description.abstract | The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 mum CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q(inv)/L-2-formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V-GS and V-DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices. (C) 2004 Elsevier Ltd. All rights reserved. | - |
dc.description.sponsorship | This work was supported by the National Program for Tera-level Nano Devices through the Ministry of Science and Technology and by MICROS center through the Korea Science and Engineering Foundation. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
dc.subject | PARAMETER-EXTRACTION | - |
dc.subject | SIMULATION | - |
dc.title | Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs | - |
dc.type | Article | - |
dc.identifier.wosid | 000224520600021 | - |
dc.identifier.scopusid | 2-s2.0-4544255194 | - |
dc.type.rims | ART | - |
dc.citation.volume | 48 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 2255 | - |
dc.citation.endingpage | 2262 | - |
dc.citation.publicationname | SOLID-STATE ELECTRONICS | - |
dc.identifier.doi | 10.1016/j.sse.2004.05.081 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Lee, Kwyro | - |
dc.contributor.nonIdAuthor | Han K. | - |
dc.contributor.nonIdAuthor | Shin H. | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | thermal noise | - |
dc.subject.keywordAuthor | MOSFET | - |
dc.subject.keywordAuthor | RF CMOS | - |
dc.subject.keywordAuthor | velocity saturation effect | - |
dc.subject.keywordAuthor | carrier heating | - |
dc.subject.keywordAuthor | inversion charge | - |
dc.subject.keywordAuthor | channel length | - |
dc.subject.keywordAuthor | modulation | - |
dc.subject.keywordPlus | PARAMETER-EXTRACTION | - |
dc.subject.keywordPlus | SIMULATION | - |
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