Proposal of a ferroelectric multi-bit memory structure for reliable operation at sub-100 nm scale

Abstract

Although ferroelectric materials are attractive due to their non-volatility originating from their spontaneous polarisation, advances in integrated density of these materials are required. To overcome the poor integration density compared with silicon integrated circuits, the concept of multi-bit memory has arisen. Previous ferroelectric multi-bit memory devices were developed through the realisation of a framework of two laterally neighbouring capacitors, in which both capacitors have different thicknesses for individual switching in different voltage ranges. However, a reliability issue with regard to limiting the additional scale down of these materials to the sub-100 nm level arose due to self-crosstalk, which was defined as a protrusion of the electric fringing field when a logic state was written in a multi-bit memory device. Here, self-crosstalk by simulating an electric field distribution in a multi-bit memory cell based on an actual sample fabricated with a ferroelectric polymer, after which they suggest a new three-dimensional structure of the ferroelectric multi-bit memory device to eliminate self-crosstalk.