Novel Sidewall Interconnection Using a Perpendicular Circuit Die for 3-D Chip Stacking

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A new sidewall interconnection approach using a perpendicular circuit die is implemented in this paper; this device can be applied to the fabrication of chip stacks. Thermal stress analysis is implemented using the ABAQUS software package to investigate the reliability issues of a stacked chip. The analysis indicates that it has little effect on the reliability of the stacked chip. Experiments were conducted by stacking four chips each having a thickness of 180 mu m; the configuration of the pads on the test chip is similar to that of a memory chip. The stacked chips were fabricated successfully by dicing the wafer. Vertical interconnection was made by thermo-compression bonding a perpendicular circuit die on an edge of the chip stack. The interconnection quality of the stacked chip was examined through 3-D images obtained via Computed Tomography (CT) and X-ray imagery. The images show that the interconnections were made successfully. The electrical contact resistance of the interconnection is comparable with that obtained using the wire bonding.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2015-09
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.5, no.9, pp.1265 - 1272

ISSN
2156-3950
DOI
10.1109/TCPMT.2015.2457419
URI
http://hdl.handle.net/10203/205346
Appears in Collection
ME-Journal Papers(저널논문)
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