A 4.9mW Neural Network Task Scheduler for Congestion-Minimized Network-on-Chip in Multi-Core Systems
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yoo, Hoi-Jun | ko |
| dc.contributor.author | Kim, Youchang | ko |
| dc.contributor.author | Kim, Gyeonghoon | ko |
| dc.contributor.author | Hong, Injoon | ko |
| dc.contributor.author | Kim, Donghyun | ko |
| dc.date.accessioned | 2016-04-18T05:24:44Z | - |
| dc.date.available | 2016-04-18T05:24:44Z | - |
| dc.date.created | 2015-11-18 | - |
| dc.date.created | 2015-11-18 | - |
| dc.date.issued | 2014-11-12 | - |
| dc.identifier.citation | IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.213 - 216 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/204604 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A 4.9mW Neural Network Task Scheduler for Congestion-Minimized Network-on-Chip in Multi-Core Systems | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-84922558575 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 213 | - |
| dc.citation.endingpage | 216 | - |
| dc.citation.publicationname | IEEE Asian Solid-State Circuits Conference (A-SSCC) | - |
| dc.identifier.conferencecountry | CH | - |
| dc.contributor.localauthor | Yoo, Hoi-Jun | - |
| dc.contributor.nonIdAuthor | Kim, Gyeonghoon | - |
| dc.contributor.nonIdAuthor | Kim, Donghyun | - |
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