Reducing routing congestion and chip area by post placement optimization utilizing redundant inter-cell margin
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 정우현 | ko |
| dc.contributor.author | 심성보 | ko |
| dc.contributor.author | 신영수 | ko |
| dc.date.accessioned | 2016-04-18T05:21:58Z | - |
| dc.date.available | 2016-04-18T05:21:58Z | - |
| dc.date.created | 2015-11-23 | - |
| dc.date.issued | 2015-02-10 | - |
| dc.identifier.citation | 한국반도체학술대회 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/204574 | - |
| dc.language | English | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | Reducing routing congestion and chip area by post placement optimization utilizing redundant inter-cell margin | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | 한국반도체학술대회 | - |
| dc.identifier.conferencecountry | KO | - |
| dc.identifier.conferencelocation | 인천 송도 컨벤시아 | - |
| dc.contributor.localauthor | 신영수 | - |
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.