7.4 mu W Ultra-High Slew-rate Pseudo Single-Stage Amplifier Driving 0.1-to-15nF Capacitive Load with > 69 degrees Phase Margin
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Hong, Sung-Wan | ko |
| dc.contributor.author | Cho, Gyu-Hyeong | ko |
| dc.date.accessioned | 2016-04-18T05:12:36Z | - |
| dc.date.available | 2016-04-18T05:12:36Z | - |
| dc.date.created | 2015-11-22 | - |
| dc.date.created | 2015-11-22 | - |
| dc.date.issued | 2015-06-18 | - |
| dc.identifier.citation | 2015 Symposium on VLSI Circuits, SOVC 2015 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/204472 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | 7.4 mu W Ultra-High Slew-rate Pseudo Single-Stage Amplifier Driving 0.1-to-15nF Capacitive Load with > 69 degrees Phase Margin | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000370961400115 | - |
| dc.identifier.scopusid | 2-s2.0-84957888574 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | 2015 Symposium on VLSI Circuits, SOVC 2015 | - |
| dc.identifier.conferencecountry | JA | - |
| dc.identifier.conferencelocation | RIHGA Royal Hotel Kyoto | - |
| dc.contributor.localauthor | Cho, Gyu-Hyeong | - |
| dc.contributor.nonIdAuthor | Hong, Sung-Wan | - |
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