A DC-to-12.5Gb/s 4.88mW/Gb/s All-rate CDR with a single LC VCO in 90nm CMOS
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yoon, Jong Hyeok | ko |
| dc.contributor.author | Kwon, Soon Won | ko |
| dc.contributor.author | Bae, Hyeon Min | ko |
| dc.date.accessioned | 2016-04-18T04:59:13Z | - |
| dc.date.available | 2016-04-18T04:59:13Z | - |
| dc.date.created | 2015-11-20 | - |
| dc.date.created | 2015-11-20 | - |
| dc.date.created | 2015-11-20 | - |
| dc.date.issued | 2015-09-29 | - |
| dc.identifier.citation | IEEE Custom Integrated Circuits Conference (CICC) 2015, pp.1 - 4 | - |
| dc.identifier.issn | 0886-5930 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/204328 | - |
| dc.description.abstract | The proposed CDR supports reference-less all-rate operation with static fractional divider and asynchronous phase calibration scheme. And the IC features an automatic loop gain control scheme which adjusts the bandwidth of a CDR automatically in the background for optimum BER performance. The power efficiency of the test chip is 4.88mW/Gb/s. | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A DC-to-12.5Gb/s 4.88mW/Gb/s All-rate CDR with a single LC VCO in 90nm CMOS | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000369107500114 | - |
| dc.identifier.scopusid | 2-s2.0-84959220994 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 1 | - |
| dc.citation.endingpage | 4 | - |
| dc.citation.publicationname | IEEE Custom Integrated Circuits Conference (CICC) 2015 | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | DoubleTree Hotel, San Jose, California | - |
| dc.contributor.localauthor | Bae, Hyeon Min | - |
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