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Results 1-10 of 28 (Search time: 0.007 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Wallace-Tree based Timing-Driven Synthesis of Arithmetic Circuits Taewhan Kim, IEEE International Conference on VLSI and CAD (VLSICAD), pp.89 - 94, 1999 | |
| A Complete Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), 2000 | |
| Utilization of Multiport Memories in Data Path Synthesis Taewhan Kim, ACM/IEEE Design Automation Conference (DAC), pp.298 - 302, 1993 | |
| A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability Taewhan Kim, IEEE European Design and Test Conference (EDAC), pp.586 - 590, 1994 | |
| Register Allocation for Dataflow Graphs with Conditional Branches and Loops Taewhan Kim, IEEE European Design Automation Conference (Euro-DAC), pp.232 - 237, 1993 | |
| A Scheduling Algorithm for Conditional Resource Sharing Taewhan Kim, IEEE International Conference on Computer-Aided Design (ICCAD), pp.84 - 87, 1991 | |
| An Integrated Data Path Synthesis Algorithm based on Network Flow Method Taewhan Kim, IEEE Custom Integrated Circuits Conference (CICC), pp.615 - 618, 1995 | |
| A Non-Zero Delay Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000 | |
| An Efficient Data Path Synthesis Algorithm for Behavioral-level Power Optimization Taewhan Kim, IEEE International Symposium on Circuits and Systems (ISCAS), pp.I-294 - I-297, 1999 | |
| Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications Taewhan Kim, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.156 - 161, 2000 |
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Date issued
- 17 2000 - 2003
- 11 1991 - 1999