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Results 1-10 of 29 (Search time: 0.003 seconds).

NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
1
Wallace-Tree based Timing-Driven Synthesis of Arithmetic Circuits

Taewhan Kimresearcher, IEEE International Conference on VLSI and CAD (VLSICAD), pp.89 - 94, 1999

2
A Complete Model for Glitch Analysis in Logic Circuits

Taewhan Kimresearcher, IEEE International ASIC/SOC Conference (ASIC), 2000

3
Utilization of Multiport Memories in Data Path Synthesis

Taewhan Kimresearcher, ACM/IEEE Design Automation Conference (DAC), pp.298 - 302, 1993

4
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability

Taewhan Kimresearcher, IEEE European Design and Test Conference (EDAC), pp.586 - 590, 1994

5
Register Allocation for Dataflow Graphs with Conditional Branches and Loops

Taewhan Kimresearcher, IEEE European Design Automation Conference (Euro-DAC), pp.232 - 237, 1993

6
A Scheduling Algorithm for Conditional Resource Sharing

Taewhan Kimresearcher, IEEE International Conference on Computer-Aided Design (ICCAD), pp.84 - 87, 1991

7
An Integrated Data Path Synthesis Algorithm based on Network Flow Method

Taewhan Kimresearcher, IEEE Custom Integrated Circuits Conference (CICC), pp.615 - 618, 1995

8
A Non-Zero Delay Model for Glitch Analysis in Logic Circuits

Taewhan Kimresearcher, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000

9
An Efficient Data Path Synthesis Algorithm for Behavioral-level Power Optimization

Taewhan Kimresearcher, IEEE International Symposium on Circuits and Systems (ISCAS), pp.I-294 - I-297, 1999

10
Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications

Taewhan Kimresearcher, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.156 - 161, 2000

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