Browse "RIMS Conference Papers" by Author 1096

Showing results 1 to 60 of 67

1
25nm Bulk MOSFET with Floating Gate Spacer

Hyung-Cheol Shin, Silicon Nanoelectronics Workshop, pp.12 - 13, 2000

2
45 nm baised spacer MOSFET

Hyung-Cheol Shin, Silicon Nanoelectronics Workshop, pp.126 - 127, 2003

3
50 nm MOSFET with Floating Polysilicon Spacer

Hyung-Cheol Shin, IEEE Silicon Nanoelectronics Workshop, pp.54 - 55, 2001

4
50 nm MOSFET with High-k Dielectric Sidewall

Hyung-Cheol Shin, IEEE Silicon Nanoelectronics Workshop, pp.70 - 71, 2001

5
A 2.4-GHz Fully Integrated CMOS Quadrature VCO

Hyung-Cheol Shin, Asia Pacific-System on a Chip 2002, pp.207 - 210, 2002

6
A 2.4-GHz Fully Integrated CMOS Quadrature VCO

신형철, IDEC Conference 2002-Summer, pp.31 - 34, 2002

7
A 5-GHz Band I/Q Generator using a Self-Calibration Technique

Beom-Sup Kim; Hyung-Cheol Shin, European Solid-State Circuit Conference, pp.807 - 810, 2002

8
A direct method to extract the substrate resistance components of RF MOSFETs valid up to 50 GHz

Kim S.; Han J.; Shin H., 2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems: Digest of Papers, pp.235 - 238, 2004-09-08

9
A Model of Thin Oxide Damage by Plasma Etching and Ashing Processes

Hyung-Cheol Shin, Plasma Etch, pp.27 - 29, 1991

10
A nano-structure Memory with SOI Edge channel and A nano dot

Hyung-Cheol Shin, MNC(Microproceses and Nanotechnology Conference), pp.315 - 316, 1998

11
A New Curvature-Compensated CMOS Bandgap Reference with Low Power Consumption

Hyung-Cheol Shin, ITC-CSCC 2000, pp.612 - 614, 2000

12
A new RF model for the accumulation-mode MOS varactor

Song S.-S.; Shin H., 2003 IEEE MTT-S International Microwave Symposium Digest, v.2, pp.1023 - 1026, 2003-06-08

13
A New SOI Inverter using Active Body-Bias

Hyung-Cheol Shin, ITC-CSCC, pp.1457 - 1459, 1998

14
A Nonvolatile Memory Using Nanocrystals Formed by Wet Etching

Hyung-Cheol Shin, ICSMM 2000, pp.124 - 125, 2000

15
A scalable model for the substrate resistance in multi-finger RF MOSFETs

Han J.; Shin H., 2003 IEEE MTT-S International Microwave Symposium Digest, v.3, pp.2105 - 2108, 2003-06-08

16
A self-assembled silicon quantum dot transistor operation at room temperature

Hyung-Cheol Shin, 1998 ASIAN SCIENCE SEMINAR, 1998

17
A self-assembled silicon quantum dot transistor operation at room temperature

Hyung-Cheol Shin, NPMS'98, 1998

18
A self-assembled silicon quantum dot transistor operation at room temperature

Hyung-Cheol Shin, Sound Quality Symposium Conference(SQS), 1998

19
A Simple Technique to Measure Generation Lifetime in Partially Depleted SOI MOSFETS

Hyung-Cheol Shin, 5th International Conference on VLSI and CAD, pp.55 - 59, 1997

20
A Simple Wide-Band MIM Capacitor Model for RF Applications and the Effect of Substrate Grounded Shields

Hyung-Cheol Shin, 2003 International Conference on Solid State Devices and Materials (SSDM 2003), 2003

21
A Tri-Gate MOSFET with Gate-to-Source/Drain Non-overlapped Structure for 5 nm Regime

Hyung-Cheol Shin, Silicon Nanoelectronics Workshop 2003, pp.32 - 33, 2003

22
Accurate Four-Terminal RF MOSFET Model Accounting for the Short-Channel Effect in the Source-to-Drain Capacitance

Hyung-Cheol Shin, SISPAD 2003, 2003

23
Characteristics of P-channel Si Nano-crystal Memory

Hyung-Cheol Shin, IEEE Region 10 Ionference, TENCON, pp.1140 - 1142, 1999

24
Characteristics of P-channel Si Nano-crystal Memory with Tunneling Oxide

Hyung-Cheol Shin, 99 ISDRS, pp.73 - 75, 1999

25
Characteristics of Thermal Nitride Grown by IR Furnace

Hyung-Cheol Shin, IUMRS-ICEM-98, pp.106 - 106, 1998

26
Characterization of oxide Charging in a Magnetically Enhanced Rie Polysilicon Etcher

Hyung-Cheol Shin, Proc. 11th International Syposium on Plasma Chemistry, pp.1534 - 1539, 1993

27
Characterization of Process-Induced Damage During Aluminum Etching and Photoresist Ashing

Hyung-Cheol Shin, International Wafer Level Reliability Workshop, pp.133 - 144, 1991

28
Characterization of Thin Oxide Damage During Aluminum Etching and Photoresist Ashing Processes

Hyung-Cheol Shin, International Symposium on VLSI Technology,Systems and Applications, pp.210 - 213, 1991

29
Comparative Study of the De-embedding Methods for RF device

신형철, Agilent EEsof User Workshop, pp.55 - 57, 2002

30
Comparison of the characteristics of tunneling oxide and tunneling ON for P-channel Nano-crystal Memory

Hyung-Cheol Shin, The 6th International Conference on VLSI and Cad(ICVC'99), pp.233 - 236, 1999

31
DC and AC Characteristics of 10 nm T-Gate MOSFETs with Source/Drain-to-gate Non-Overlapped Structure

Hyung-Cheol Shin, Silicon Nanoelectronics Workshop 2003, pp.24 - 25, 2003

32
Device Characteristics of 25 nm MOSFET with Floating Side Gates

Hyung-Cheol Shin, ICSMM 2000, pp.118 - 119, 2000

33
Effect of Body Structure on Analog Performance of SOI NMOSFET's

Hyung-Cheol Shin, IEEE SOI Conference, pp.61 - 62, 1998

34
Fabrication and Characterization of a Quantum Dot Flash Memory

Hyung-Cheol Shin, 99 International Workshop on Advanced LSI's and Devices, pp.12 - 15, 1999

35
Fabrication of siliocon Quantum Dots on Oxide and Nitride

Hyung-Cheol Shin, MNC(Microproceses and Nanotechnology Conference), pp.136 - 137, 1998

36
Factors Affecting Charge-up in a Magnetically Enhanced RIE Polysilicon Etcher

Hyung-Cheol Shin, Proc. Electrochemical Society, pp.405 - 406, 1993

37
Gate Oxide Damage by Plasma Oxide Deposition and Via RIE

Hyung-Cheol Shin, American Vacuum Society Plasma Etch 1992 Symposium, 1992

38
High speed and low power SOI inverter using active body-bias

Gil Joonho; Je Minkyu; Lee Jongho; Shin Hyungcheol, Proceedings of the 1998 International Symposium on Low Power Electronics and Design, pp.59 - 63, 1998-08-10

39
Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide

Hyung-Cheol Shin, IEDM Technical Digest, pp.467 - 470, 1993

40
Integrity of Gate Oxide on TFSOI Materials

Hyung-Cheol Shin, Proc. IEEE International SOI Conference, pp.22 - 23, 1995

41
Lateral Silicon Field Emission Devices using Electron Beam Lithography

Hyung-Cheol Shin, Micoroprocesses and Nanotechnology'99, pp.134 - 135, 1999

42
Materials, Device and Gate Oxide Integrith Evaluation of Simox and Bonded SOI Wafers

Hyung-Cheol Shin, Proc. IEEE International SOI Conference, pp.143 - 145, 1995

43
MOS Image Sensor Cell Suppressed Blooming

신형철, Proc. of Conference of KITE, pp.308 - 311, 1987

44
MOS Memory Using Si Nanocrystals Formed by Wet Etching of Poly-Silicon Along Grain Boundaries

Hyung-Cheol Shin, 2000 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp.221 - 224, 2000

45
Optimization of Spiral Inductors on Siliocon Substrate

신형철, IDEC Conference 2002-Summer, pp.49 - 52, 2002

46
Optimization of Symmetric Spiral Inductors on Siliocon Substrate

신형철, Agilent EEsof User Workshop, pp.58 - 62, 2002

47
P-channel Nano Crystal Memory

Hyung-Cheol Shin, 2000 China-Korea Joint Symposium on Semiconductor Physics and Device Application, pp.19 - 19, 2000

48
Physical modeling of substrate resistance in RF MOSFETs

Han J.; Je M.; Shin H., 2003 Nanotechnology Conference and Trade Show - Nanotech 2003, v.2, pp.290 - 293, 2003-02-23

49
Physical Modeling of Substrate Resistance in RF MOSFETs

Hyung-Cheol Shin, Workshop on Compact Modeling at the 5th International Conference on Modeling and Simulation of Microsystems, pp.335 - 338, 2003

50
Physical RF modeling of Junction Varactors

Hyung-Cheol Shin, SSDM 2002, pp.418 - 419, 2002

51
Plasma-Etching induced Damage to Thin Oxide

Hyung-Cheol Shin, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp.79 - 83, 1992

52
PMOS-based Si Nano-crystal Memory

Hyung-Cheol Shin, Silicon nanoelectronics workshop, pp.10 - 11, 1999

53
Process-Induced Charging Damage in PETEOS for Interlevel Dielectric Applications

Hyung-Cheol Shin, International Symposium on Plasma Process-Induced Damage, pp.109 - 112, 1996

54
Programming and Erasing Characteristics of P-channel Nano-crystal Memory

Hyung-Cheol Shin, Semicon Korea Technical Symposium 2000, pp.5 - 10, 2000

55
Quantized Canductance of a Gate-All-Around Silicon Quantum Wire Transistor

Hyung-Cheol Shin, MNC(Microprocesses and Nanotechnology Conference, pp.150 - 151, 1998

56
Recessed Channel(RC) SOI NMOSFET's with Self-Aligned Polysilicon Gate Formed on the RC Region

Hyung-Cheol Shin, Proc. IEEE International SOI Conference, pp.122 - 123, 1996

57
RF characteristics of 30 nm MOSFETs with non-overlapped source-drain to gate

Hyung-Cheol Shin, Silicon Nanoelectronics Workshop 2002, 2002

58
Silicon MOS Memory with self-aligned Quantum Dot on Narow Channel

Hyung-Cheol Shin, ICVC99, pp.187 - 189, 1999

59
Silicon nano-crystal memory with tunneling nitride

Hyung-Cheol Shin, International Conference on Solid State Devices and Materials, pp.170 - 171, 1998

60
Sub 4-nm Polyoxide Using ECR(Electron Cyclotron Resonance) N2O Plasma Oxidation

Hyung-Cheol Shin, 2000 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp.25 - 30, 2000

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