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Coupling delay optimization by temporal decorrelation using dual threshold voltage technique Kim, KW; Jung, SO; Kim, Taewhan; Saxena, P; Liu, CL; Kang, SM, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.11, pp.879 - 887, 2003-10 |
Minimum delay optimization for domino logic circuits - A coupling-aware approach Kim, KW; Jung, SO; Kim, Taewhan; Kang, SM, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.8, pp.203 - 213, 2003-04 |
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