Leakage current limit of time domain reflectometry in ultrathin dielectric characterization

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dc.contributor.authorKim, Yonghunko
dc.contributor.authorBaek, Seung Heonko
dc.contributor.authorJeon, Chang Hoonko
dc.contributor.authorLee, Young Gonko
dc.contributor.authorKim, Jin Juko
dc.contributor.authorJung, Ukjinko
dc.contributor.authorKang, Soo Cheolko
dc.contributor.authorPark, Woojinko
dc.contributor.authorLee, Seok-Heeko
dc.contributor.authorLee, Byoung Hunko
dc.date.accessioned2015-11-20T09:53:19Z-
dc.date.available2015-11-20T09:53:19Z-
dc.date.created2014-10-27-
dc.date.created2014-10-27-
dc.date.issued2014-08-
dc.identifier.citationJAPANESE JOURNAL OF APPLIED PHYSICS, v.53, no.8, pp.37 - 41-
dc.identifier.issn0021-4922-
dc.identifier.urihttp://hdl.handle.net/10203/201158-
dc.description.abstractThe accurate characterization of highly leaky dielectrics has been a serious challenge in MOSFET and capacitor studies. We have shown that time domain reflectometry (TDR) can be used to measure the capacitance of ultrathin SiO2 MOS capacitors even at a leakage current density as high as similar to 3000 A/cm(2), which is approximately 10(3) times higher than the limit of a conventional impedance analyzer. The extremely short interaction time of the TDR C-V method makes the TDR capacitance measurement more immune to the leakage current. Since the TDR C-V method does not require special high-frequency test structures other than a ground-signal pad pattern, the TDR C-V method is a promising capacitance measurement method for leaky dielectrics.-
dc.languageEnglish-
dc.publisherIOP PUBLISHING LTD-
dc.subjectCAPACITANCE-VOLTAGE MEASUREMENT-
dc.subjectGATE OXIDE-
dc.subjectINTERFACE-
dc.subjectTHICKNESS-
dc.subjectMOSFETS-
dc.subjectSEMICONDUCTOR-
dc.subjectRELIABILITY-
dc.subjectPERFORMANCE-
dc.subjectEXTRACTION-
dc.subjectCIRCUIT-
dc.titleLeakage current limit of time domain reflectometry in ultrathin dielectric characterization-
dc.typeArticle-
dc.identifier.wosid000342523700009-
dc.identifier.scopusid2-s2.0-84906063048-
dc.type.rimsART-
dc.citation.volume53-
dc.citation.issue8-
dc.citation.beginningpage37-
dc.citation.endingpage41-
dc.citation.publicationnameJAPANESE JOURNAL OF APPLIED PHYSICS-
dc.identifier.doi10.7567/JJAP.53.08LC02-
dc.contributor.localauthorLee, Seok-Hee-
dc.contributor.nonIdAuthorKim, Yonghun-
dc.contributor.nonIdAuthorLee, Young Gon-
dc.contributor.nonIdAuthorKim, Jin Ju-
dc.contributor.nonIdAuthorJung, Ukjin-
dc.contributor.nonIdAuthorKang, Soo Cheol-
dc.contributor.nonIdAuthorPark, Woojin-
dc.contributor.nonIdAuthorLee, Byoung Hun-
dc.type.journalArticleArticle-
dc.subject.keywordPlusCAPACITANCE-VOLTAGE MEASUREMENT-
dc.subject.keywordPlusGATE OXIDE-
dc.subject.keywordPlusINTERFACE-
dc.subject.keywordPlusTHICKNESS-
dc.subject.keywordPlusMOSFETS-
dc.subject.keywordPlusSEMICONDUCTOR-
dc.subject.keywordPlusRELIABILITY-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusEXTRACTION-
dc.subject.keywordPlusCIRCUIT-
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