A Core Compact Model for Multiple-Gate Junctionless FETs

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dc.contributor.authorHur, Jaeko
dc.contributor.authorMoon, Dong-Ilko
dc.contributor.authorChoi, Ji-Minko
dc.contributor.authorSeol, Myeong-Lokko
dc.contributor.authorJeong, Ui-Sikko
dc.contributor.authorJeon, Chang-Hoonko
dc.contributor.authorChoi, Yang-Kyuko
dc.date.accessioned2015-07-22T05:17:48Z-
dc.date.available2015-07-22T05:17:48Z-
dc.date.created2015-06-21-
dc.date.created2015-06-21-
dc.date.created2015-06-21-
dc.date.issued2015-07-
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.62, no.7, pp.2285 - 2291-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10203/200080-
dc.description.abstractA core model for multiple-gate junctionless FETs (Mug-JL-FETs) is proposed. The derived charge model is obtained via assumptions of simple potential profile for different types of Mug-JL-FETs. It was found that the linear potential approach is not accurate enough for a double-gate (DG) JL-FET, whereas it was reasonably precise for a DG inversion-mode FET. This discrepancy arises from their different operating mechanisms. Thus, the parabolic potential assumption, which is intuitively close to an actual potential profile in the Mug-FETs, was applied. As a consequence, two different formulas of the charge model in terms of depletion charges, gate capacitance, and capacitance inside the channel were found: one for a tetragonal shape of a cross-sectional channel based on a Cartesian coordinate and the other for a circular shape of a cross-sectional channel based on a cylindrical coordinate. Moreover, the proposed approach was applied for a realistically shaped channel, which is close to elliptic geometry, with a circular profile at the top and bottom parts of the channel and a rectangular profile at the center part of the channel. By applying the decoupling method reported previously, a drain current model, which is extended from the above-mentioned charge model, was also obtained.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectNANOWIRE TRANSISTORS-
dc.subjectMOSFETS-
dc.subjectCHANNEL-
dc.subjectBODY-
dc.titleA Core Compact Model for Multiple-Gate Junctionless FETs-
dc.typeArticle-
dc.identifier.wosid000356457900032-
dc.identifier.scopusid2-s2.0-85027922249-
dc.type.rimsART-
dc.citation.volume62-
dc.citation.issue7-
dc.citation.beginningpage2285-
dc.citation.endingpage2291-
dc.citation.publicationnameIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.identifier.doi10.1109/TED.2015.2428711-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.contributor.nonIdAuthorJeong, Ui-Sik-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorCore model-
dc.subject.keywordAuthorcylindrical gate-all-around (Cy-GAA) FET-
dc.subject.keywordAuthordouble-gate (DG) FET-
dc.subject.keywordAuthorjunctionless FET (JL-FET)-
dc.subject.keywordAuthormultiple gate-
dc.subject.keywordAuthorrectangular gate-all-around FET (Re-GAA-FET)-
dc.subject.keywordAuthortriple-gate FET (TG-FET)-
dc.subject.keywordPlusNANOWIRE TRANSISTORS-
dc.subject.keywordPlusMOSFETS-
dc.subject.keywordPlusCHANNEL-
dc.subject.keywordPlusBODY-
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