DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hur, Jae | ko |
dc.contributor.author | Moon, Dong-Il | ko |
dc.contributor.author | Choi, Ji-Min | ko |
dc.contributor.author | Seol, Myeong-Lok | ko |
dc.contributor.author | Jeong, Ui-Sik | ko |
dc.contributor.author | Jeon, Chang-Hoon | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2015-07-22T05:17:48Z | - |
dc.date.available | 2015-07-22T05:17:48Z | - |
dc.date.created | 2015-06-21 | - |
dc.date.created | 2015-06-21 | - |
dc.date.created | 2015-06-21 | - |
dc.date.issued | 2015-07 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.62, no.7, pp.2285 - 2291 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/200080 | - |
dc.description.abstract | A core model for multiple-gate junctionless FETs (Mug-JL-FETs) is proposed. The derived charge model is obtained via assumptions of simple potential profile for different types of Mug-JL-FETs. It was found that the linear potential approach is not accurate enough for a double-gate (DG) JL-FET, whereas it was reasonably precise for a DG inversion-mode FET. This discrepancy arises from their different operating mechanisms. Thus, the parabolic potential assumption, which is intuitively close to an actual potential profile in the Mug-FETs, was applied. As a consequence, two different formulas of the charge model in terms of depletion charges, gate capacitance, and capacitance inside the channel were found: one for a tetragonal shape of a cross-sectional channel based on a Cartesian coordinate and the other for a circular shape of a cross-sectional channel based on a cylindrical coordinate. Moreover, the proposed approach was applied for a realistically shaped channel, which is close to elliptic geometry, with a circular profile at the top and bottom parts of the channel and a rectangular profile at the center part of the channel. By applying the decoupling method reported previously, a drain current model, which is extended from the above-mentioned charge model, was also obtained. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | NANOWIRE TRANSISTORS | - |
dc.subject | MOSFETS | - |
dc.subject | CHANNEL | - |
dc.subject | BODY | - |
dc.title | A Core Compact Model for Multiple-Gate Junctionless FETs | - |
dc.type | Article | - |
dc.identifier.wosid | 000356457900032 | - |
dc.identifier.scopusid | 2-s2.0-85027922249 | - |
dc.type.rims | ART | - |
dc.citation.volume | 62 | - |
dc.citation.issue | 7 | - |
dc.citation.beginningpage | 2285 | - |
dc.citation.endingpage | 2291 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2015.2428711 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Jeong, Ui-Sik | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Core model | - |
dc.subject.keywordAuthor | cylindrical gate-all-around (Cy-GAA) FET | - |
dc.subject.keywordAuthor | double-gate (DG) FET | - |
dc.subject.keywordAuthor | junctionless FET (JL-FET) | - |
dc.subject.keywordAuthor | multiple gate | - |
dc.subject.keywordAuthor | rectangular gate-all-around FET (Re-GAA-FET) | - |
dc.subject.keywordAuthor | triple-gate FET (TG-FET) | - |
dc.subject.keywordPlus | NANOWIRE TRANSISTORS | - |
dc.subject.keywordPlus | MOSFETS | - |
dc.subject.keywordPlus | CHANNEL | - |
dc.subject.keywordPlus | BODY | - |
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