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A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation Jo, Youngwoo; Kim, Hyo Jun; Cho, Seonghwan, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.26, no.10, pp.2170 - 2174, 2018-10 |
A three-dimensional stacked-chip star-wiring interconnection for a digital noise-free and low-jitter I/O clock distribution network Ryu, C; Chung, D; Lee, C; Kim, Joungho; Bae, K; Yu, J; Lee, S, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.16, pp.651 - 653, 2006-12 |
Circuits and methods to suppress on-chip power supply noise = 칩 내부 전원선 잡음 제거를 위한 회로 및 기법에 관한 연구link Cheong, Heon-Su; 정헌수; et al, 한국과학기술원, 2010 |
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