Browse "School of Electrical Engineering(전기및전자공학부)" by Subject GATE STACK
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| Border-trap characterization in high-kappa strained-si MOSFETs Maji, Debabrata; Duttagupta, S. P.; Rao, V. Rarngopal; Yeo, Chia Ching; Cho, Byung Jin, IEEE ELECTRON DEVICE LETTERS, v.28, no.8, pp.731 - 733, 2007-08 |
| Lowering the effective work function via oxygen vacancy formation on the GeO2/Ge interface Lee, Tae In; Seo, Yujin; Moon, Jung Min; Ahn, Hyunjun; Yu, Hyun-Young; Hwang, Wan Sik; Cho, Byung Jin, SOLID-STATE ELECTRONICS, v.130, pp.57 - 62, 2017-04 |
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