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Showing results 22 to 59 of 59

22	Leakage control through fine-grained power gating: methodology and implementation Knebel, D; Kosonocky, S; Bhattacharya, S; Puri, R; Shin, Youngsoo, IBM Austin Conference on Energy-Efficient Design (ACEED), IBM, 2004
23	Leakage-Aware Technology Mapping for Sequential Circuits 허세완; 신영수, 제 14회 한국반도체학술대회, 2007-02-08
24	Long-Term Power Minimization of Dual-Vt CMOS Circuits Kim, S; Shin, Youngsoo; Kosonocky, S; Hwang, W., Int'l ASIC/SOC Conf., pp.323 - 327, IEEE, 2002-09
25	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops Kim, J.; Shin, Youngsoo, 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, pp.797 - 802, 2007-11-04
26	Modeling and analysis of power for System-on-a-Chip design Nair, I.I.; Shin, Youngsoo; Bergamaschi, R.A.; Bhattacharya, S; Darringer, J; Kosonocky, S, IBM Austin Conference on Energy-Efficient Design (ACEED), IBM, 2003-03
27	Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements Paik, S.; Shin, Youngsoo, 45th Design Automation Conference, DAC, pp.600 - 605, 2008-06-08
28	Narrow bus encoding for low power systems Shin, Youngsoo; Choi, K, Asia South Pacific Design Automation Conf. (ASPDAC), pp.217 - 220, ACM Press, 2000-01
29	Partial bus-invert coding for power optimization of system level bus Shin, Youngsoo; Chae, SI; Choi, K, Symp. on Low Power Electronics and Design (ISLPED), pp.127 - 129, ACM Press, 1998-08
30	Physical design methodology for power gating circuits with transparent use of standard cells 김형옥; 신영수, 한국반도체학술대회, pp.877 - 878, 2006
31	Placement optimization for MP-DSAL compliant layout Shim, Seongbo; Chung, Woohyun; Shin, Youngsoo, IEEE International Conference on IC Design and Technology (ICICDT), IEEE/ACM, 2016-06-27
32	Power conscious fixed priority scheduling for hard real-time systems Shin, Youngsoo; Choi, K, Design Automation Conf. (DAC), pp.134 - 139, 1999-06
33	Power gating and supply control for low standby leakage power of VLSI circuits Heo, S; Kim, HO; Shin, Youngsoo, Symposium on Low-Power and High-Speed Chips (COOL Chips), pp.305 - 307, IEEE, 2006-04
34	Power Optimization of Real-Time Embedded Systems on Variable Speed Processors Shin, Youngsoo; Choi, K; Sakurai, T, IEEE/ACM International Conference on Computer Aided Design, pp.365 - 368, IEEE, 2000-11
35	Power-gating-aware high-level synthesis Choi, E.; Shin, C.; Kim, T.; Shin, Youngsoo, ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, pp.39 - 44, 2008-08-11
36	Pulsed-latch circuits to push the envelope of ASIC design Paik, S.; Shin, Youngsoo, 2010 International SoC Design Conference, ISOCC 2010, pp.150 - 153, ISOCC 2010, 2010-11-22
37	Rate assignment for embedded reactive real-time systems Shin, Youngsoo; Choi, K, Euromicro Workshop on Digital Systems Design, pp.237 - 242, 1998
38	Register grouping for synthesis of clock gating logic Han, In-Hak; Kim, Jongkyou; Yi, Junhwan; Shin, Youngsoo, IEEE International Conference on IC Design and Technology (ICICDT), IEEE/ACM, 2016-06-27
39	Schedulability-driven performance analysis of multiple mode embedded real-time systems Shin, Youngsoo; Kim, D; Choi, K, Design Automation Conf. (DAC), pp.495 - 500, ACM Press, 2000-06
40	SEAS: a system for early analysis of SoCs Bergamaschi, R.A.; Shin, Youngsoo; Dhanwada, N; Bhattacharya, S; Dougherty, W.E.; Nair, I.I.; Darringer, J; et al, Int'l Conf. on Hardware/Software Codesign and System Synthesis, pp.150 - 155, ACM Press, 2003-10
41	Selectively patterned masks: Beyond structured ASIC Baek, D.; Shin, I.; Paik, S.; Shin, Youngsoo, 2010 International SoC Design Conference, ISOCC 2010, pp.154 - 157, ISOCC 2010, 2010-11-22
42	Simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits Shin, Youngsoo; Heo, S.; Kim, H.-O.; Choi, J.Y., ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, pp.654 - 659, 2007-01-23
43	Simultaneous exploration of power, physical design, and architectural performance dimensions of SoC design space using SEAS Dhanwada, N.; Bergamaschi, R.; Dungan, W.; Nair, I.; Dougherty, W.; Shin, Youngsoo; Bhattacharya, S.; et al, IP Based SoC Design Forum & Exhibition (IP-SoC), 2004-12
44	Skewed flip-flop transformation for minimizing leakage in sequential circuits Seomun, J.; Kim, J.; Shin, Youngsoo, 2007 44th ACM/IEEE Design Automation Conference, DAC'07, pp.103 - 106, 2007-06-04
45	Software Synthesis through Task Decomposition by Dependency Analysis Shin, Youngsoo; Choi, K, International Conference on Computer-Aided Design (ICCAD), pp.98 - 102, IEEE, 1996-11
46	Supply switching with ground collapse: an alternative to power gaintg for low leakage cell-based design Shin, Y; Kim, HO; Choi, B; Heo, S, 한국반도체학술대회, 2007
47	Synthesis of dual-mode circuits through optimizing transition time constraints Kim, Sang-Min; Chang, Ik Joon; Shin, Youngsoo, International Conference on Consumer Electronics, IEEE, 2016-10-26
48	Thermal signature: 자동 floorplanning을 위한 빠르고 정확한 온도 지표 신영수, 한국반도체학술대회, 한국반도체학회, 2011
49	Thread-based software synthesis for embedded system design Shin, Youngsoo; Choi, K, Proc. European Design & Test Conf. (ED&TC), , pp.282 - 286, ACM Press, 1996-03
50	Timing analysis algorithm for clock gated DETFF based circuits 모민영; 김상민; 신영수, 한국반도체학술대회, 한국반도체학회, 2011-02
51	Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating Oh, C.; Kim, S.; Shin, Youngsoo, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp.59 - 62, 2009-05-18
52	Wakeup synthesis and its buffered tree construction for power gating circuit designs Paik, S.; Kim, S.; Shin, Youngsoo, 16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10, pp.413 - 418, ACM/IEEE, 2010-08-18
53	고성능 ASIC 설계를 위한 펄스래치회로 최적화기법 분석 백승훈; 신영수, 한국반도체학술대회, 한국반도체학회, 2011-02
54	내장형 시스템 설계 환경에서의 스레드에 기초한 소프트웨어 합성 신영수; 최기영, 대한전자공학회 추계종합학술대회, v.18, no.2, pp.1085 - 1088, 대한전자공학회, 1995
55	동작모드 파워 게이팅 회로를 위한 클라 게이팅 합성 기법 신영수, 대한전자공학회 하계종합학술대회, 대한전자공학회, 2011-06
56	선택적 부분 패터닝과 이를 이용한 structured ASIC 설계 백돈규; 김덕환; 신영수, 한국반도체학술대회, 한국반도체학회, 2011-02-17
57	이종구조를 갖는 programmable logic의 routability를 개선하기 위한 패킹 알고리즘 신영수, 대한전자공학회 하계종합학술대회, 대한전자공학회, 2011-06
58	이질적 시스템 설계를 위한 소프트웨어 합성 신영수; 최기영, 대한전자공학회 학술발표회, pp.70 - 76, 대한전자공학회, 1996
59	지그재그 파워 게이팅 회로의 셀-기반 세미커스텀 설계 김형옥; 신영수, 한국반도체학술대회, 2007-02-08

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