Showing results 1 to 5 of 5
A nanowire transistor for high performance logic and terabit non-volatile memory devices Lee, H.; Ryu, S.-.W.; Han, J.-.W.; Yu, L.-E.; Im, M.; Kim, C.; Kim, S.; et al, 2007 Symposium on VLSI Technology, VLSIT 2007, pp.144 - 145, IEEE, 2007-06-12 |
Fast Monte Carlo method via reduced sample number and node filtering Han, I.; Yu, L.-E.; Shin, Youngsoo, 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010, pp.126 - 129, IEEE, 2010-06-02 |
Statistical time borrowing for pulsed-latch circuit designs Paik, S.; Yu, L.-E.; Shin, Youngsoo, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, pp.675 - 680, ASP-DAC 2010, 2010-01-18 |
Sub-5nm all-around gate FinFET for ultimate scaling Lee, H.; Yu, L.-E.; Ryu, S.-W.; Han, J.-W.; Jeon, K.; Jang, D.-Y.; Kim, K.-H.; et al, 2006 Symposium on VLSI Technology, VLSIT, pp.58 - 59, 2006-06-13 |
Timing yield estimation with clock network correlations by propagating discrete probability distributions Yu, L.-E.; Shin ,C.; Liou, J.-J.; Shin, Youngsoo, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp.63 - 66, 123, 2009-05-18 |
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