Browse "School of Electrical Engineering(전기및전자공학부)" by Author Yu, J
Showing results 1 to 3 of 3
| A three-dimensional stacked-chip star-wiring interconnection for a digital noise-free and low-jitter I/O clock distribution network Ryu, C; Chung, D; Lee, C; Kim, Joungho; Bae, K; Yu, J; Lee, S, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.16, pp.651 - 653, 2006-12 |
| High Speed and Low Noise Packaging Design Methodologies for 40 Gbps SerDes Channel with PBGA Type Package Kam, DG; Yu, J; Choi, H; Bae, K; Kim, J; Jeong, D.-K; Lee, C; et al, PIERS2006 conference, pp.128 - 128, PIERS, 2006-03-26 |
| Packaging a 40-Gbps serial link using a wire-bonded plastic ball grid array Kam, DG; Kim, Joungho; Yu, J; Choi, H; Bae, K; Lee, C, IEEE DESIGN & TEST OF COMPUTERS, v.23, pp.212 - 219, 2006-05 |
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