Browse "School of Electrical Engineering(전기및전자공학부)" by Author Yim, JS
Showing results 1 to 8 of 8
| C-based RTL design verification methodology for complex microprocessor Yim, JS; Hwang, YH; Park, CJ; Choi, H; Yang, WS; Oh, HS; Park, In-Cheol; et al, Proceedings of the 1997 34th Design Automation Conference, pp.83 - 88, 1997-06-09 |
| Control signal layout ordering scheme minimising cross-coupling effect in deep-submicrometre datapath design Yim, JS; Kyung, Chong-Min, ELECTRONICS LETTERS, v.35, no.18, pp.1542 - 1543, 1999-09 |
| Datapath layout compiler using bit-wise cell-sizing scheme for delay balancing and power minimisation Yim, JS; Kyung, Chong-Min, ELECTRONICS LETTERS, v.35, no.21, pp.1788 - 1789, 1999-10 |
| Datapath layout optimisation using genetic algorithm and simulated annealing Yim, JS; Kyung, Chong-Min, IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, v.145, no.2, pp.135 - 141, 1998-03 |
| Design verification of complex microprocessors Yim, JS; Park, CJ; Park, In-Cheol; Kyung, Chong-Min, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.7, no.4, pp.301 - 318, 1997-08 |
| SEWD: A cache architecture to speed up the misaligned instruction prefetch Yim, JS; Park, In-Cheol; Kyung, Chong-Min, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E80D, no.7, pp.742 - 745, 1997-07 |
| Single cycle access cache for the misaligned data and instruction prefetch Yim, JS; Lee, HC; Kim, TH; Park, BI; Park CJ; Park, In-Cheol, 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.677 - 678, 1997-01-28 |
| Verification methodology of compatible microprocessors Yim, JS; Park, CJ; Yang, WS; Oh, HS; Lee, HC; Choi, H; Kim, TH; et al, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.173 - 180, 1997-01-28 |
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