Browse "School of Electrical Engineering(전기및전자공학부)" by Author Yim, J.S.
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| A Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs Kyung, Chong-Min; Yim, J.S., 36th Design Automation Conference(DAC), pp.766 - 771, 1999-06 |
| Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design Kyung, Chong-Min; Yim, J.S., 36th Design Automation Conference(DAC), pp.485 - 490, 1999-06 |
| Track Minimization for the Datapath Layout Compiler Using the Hybrid Genetic Algorithm and Simulated Annealing Kyung, Chong-Min; Yim, J.S., SASIMI'98, pp.39 - 43, 1998-10 |
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