Browse "School of Electrical Engineering(전기및전자공학부)" byAuthorYeo, Chia Ching

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Border-trap characterization in high-kappa strained-si MOSFETs

Maji, Debabrata; Duttagupta, S. P.; Rao, V. Rarngopal; Yeo, Chia Ching; Cho, Byung Jinresearcher, IEEE ELECTRON DEVICE LETTERS, v.28, no.8, pp.731 - 733, 2007-08

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