Browse "School of Electrical Engineering(전기및전자공학부)" by Author Woo, R.
Showing results 1 to 13 of 13
| 480ps 64-bit Race Logic adder Lee, S.-J.; Woo, R.; Yoo, Hoi-Jun, 2001 VLSI Circuits Symposium, pp.27 - 28, IEEE, 2001-06-14 |
| A 120mW embedded 3D graphics rendering engine with 6Mb logically local frame-buffer and 3.2GByte/s run-time reconfigurable bus for PDA-chip Woo, R.; Yoon, C.-W.; Kook, J.; Lee, S.-J.; Lee, K.; Park, Y.-H.; Yoo, Hoi-Jun, 2001 VLSI Circuits Symposium, pp.95 - 98, IEEE, 2001-06-14 |
| A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications Woo, R.; Cho,i S.; Sohn, J.-H.; Song, S.-J.; Bae, Y.-D.; Yoon, C.-W.; Nam, B.-G.; et al, 2003 Digest of Technical Papers, 2003-02-09 |
| A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS Park, Y.-H.; Han, S.-H.; Kim, J.-S.; Lee, S.-J.; Kook, J.-H.; Lim, J.-W.; Woo, R.; et al, 2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC, pp.242 - 243, 2000-02-07 |
| A 80/20MHz 160mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications Yoon, C.-W.; Woo, R.; Kook, J.; Lee, S.-J.; Lee, K.; Bae, Y.-D.; Park, In-Cheol; et al, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.142 - 143441, 2001-02-05 |
| A Comparative Analysis of a DDR-SDRAM and a D-RDRAM usind a POPeye Simulator Yoo, Hoi-Jun; Lee, K.; Yoon, C.W.; Woo, R.; Kook, J., IEEE International Symposium on Circuits and Systems, pp.v81 - v84, IEEE, 2001 |
| A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator Lee, K.; Yoon, C.-W.; Woo, R.; Kook, J.-H.; Koo, J.-I.; Jung, T.-S.; Yoo, Hoi-Jun, IEEE International Symposium on Circuits and Systems (ISCAS 2001), v.5, pp.81 - 84, IEEE, 2001-05-06 |
| A fixed-point multimedia co-processor with 50Mvertices/s programmable SIMP vertex shader for mobile applications Sohn, J.-H.; Woo, J.-H.; Woo, R.; Yoo, Hoi-Jun, ESSCIRC 2005: 31st European Solid-State Circuits Conference, pp.207 - 210, 2005-09-12 |
| A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications Woo, R.; Choi, S.; Sohn, J.-H.; Song, S.-J.; Bae, Y.-D.; Yoo, Hoi-Jun, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, pp.533 - 534, 2004-01-27 |
| A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications Sohn, J.-H.; Woo, R.; Yoo, Hoi-Jun, 19th Eurographics/SIGGRAPH Graphics Hardware Workshop, Graphics Hardware 2004, pp.107 - 114, 2004-08-29 |
| A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth Park, S.-J.; Kim, J.-S.; Woo, R.; Lee, S.-J.; Lee, K.-M.; Yang, T.-H.; Jung, J.-Y.; et al, 2001 VLSI Circuits Symposium, pp.233 - 236, IEEE, 2001-06-14 |
| Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications Yoon, C.-W.; Kook, J.; Woo, R.; Lee, S.-J.; Lee, K.; Yoo, Hoi-Jun, 2001 VLSI Circuits Symposium, pp.99 - 102, IEEE, 2001-06-14 |
| Optimization of portable system architecture for real-time 3D graphics Sohn, J.-H.; Woo, R.; Yoo, Hoi-Jun, 2002 IEEE International Symposium on Circuits and Systems, pp.769 - 772, IEEE, 2002-05-26 |
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