Browse "School of Electrical Engineering(전기및전자공학부)" by Author Sim, Jaehyeong
Showing results 1 to 22 of 22
| A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices Choi, Seungkyu; Sim, Jaehyeong; Kang, Myeonggu; Choi, Yeongjae; Kim, Hyeonuk; Kim, Lee-Sup, 2019 IEEE Asian Solid-State Circuits Conference, IEEE/SSCS, 2019-11-05 |
| A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator Lee, Taeho; Kim, Yonghun; Sim, Jaehyeong; Park, Jun-Seok; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.4, pp.1450 - 1459, 2016-04 |
| A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Netwarks Kim, Hyeonuk; Sim, Jaehyeong; Choi, Yeongjae; Kim, Lee-Sup, 54th ACM/EDAC/IEEE Design Automation Conference (DAC), ACM Special Interest Group on Design Automation (SIGDA), 2017-06 |
| A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks Shin, Hyein; Sim, Jaehyeong; Lee, Daewoong; Kim, Lee-Sup, 2019 ACM/IEEE International Conference On Computer Aided Design, IEEE/ACM, 2019-11-06 |
| An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS Sim, Jaehyeong; Lee, Somin; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.1, pp.87 - 100, 2020-01 |
| An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In-Situ Personalization on Smart Devices Choi, Seungkyu; Sim, Jaehyeong; Kang, Myeonggu; Choi, Yeongjae; Kim, Hyeonuk; Kim, Lee-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.55, no.10, pp.2691 - 2702, 2020-10 |
| An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM Kim, Kyeonghan; Shin, Hyein; Sim, Jaehyeong; Kang, Myeonggu; Kim, Lee-Sup, 38th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2019, IEEE/ACM, 2019-11-06 |
CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator Choi, Yeongjae; Sim, Jaehyeong; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.12, pp.3337 - 3341, 2020-12 |
| Energy efficient processors and In-DRAM processing framework for deep convolutional neural network = 에너지 효율적인 심층 컨볼루셔널 신경망 프로세서 및 DRAM 내부 연산 프레임워크link Sim, Jaehyeong; Kim, Lee-Sup; et al, 한국과학기술원, 2019 |
| Energy-Efficient Design of Processing Element for Convolutional Neural Network Choi, Yeongjae; Bae, Dongmyung; Sim, Jaehyeong; Choi, Seungkyu; Kim, Minhye; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.11, pp.1332 - 1336, 2017-11 |
| eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators Jung, Youngbeom; Choi, Yeongjae; Sim, Jaehyeong; Kim, Lee-Sup, 38th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2019, IEEE/ACM, 2019-11-04 |
| NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks Kim, Hyeonuk; Sim, Jaehyeong; Choi, Yeongjae; Kim, Lee-Sup, 2019 IEEE International Symposium on High-Performance Computer Architecture, pp.661 - 673, IEEE/ACM, 2019-02 |
| Neural network method and apparatus Kim, Lee-Sup; Lee, Sehwan; Sim, Jaehyeong; Kim, Hyeonuk; Choi, Yeongjae |
| Neural network method and apparatus Kim, Lee-Sup; Kim, Hyeonuk; Sim, Jaehyeong; Choi, Yeongjae; Lee, Sehwan |
| NID: Processing Binary Convolutional Neural Network in Commodity DRAM Sim, Jaehyeong; Seol, Hoseok; Kim, Lee-Sup, 2018 ACM/IEEE International Conference On Computer Aided Design, pp.10:1 - 10:8, IEEE/ACM, 2018-11-05 |
| PowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field Theory Paek, Seungwook; Shin, Wongyu; Sim, Jaehyeong; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.32, no.10, pp.1509 - 1519, 2013-10 |
| PowerField: a transient temperature-to-power technique based on Markov random field theory Paek, Seungwook; Moon, Seok-Hwan; Shin, Wongyu; Sim, Jaehyeong; Kim, Lee-Sup, 2012 Design Automation Conference (DAC), pp.630 - 635, ACM/IEEE, 2012-06-06 |
| S-FLASH: A NAND Flash-based Deep Neural Network Accelerator Exploiting Bit-level Sparsity Kang, Myeonggu; Kim, Hyeonuk; Shin, Hyein; Sim, Jaehyeong; Kim, Kyeonghan; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.71, no.6, pp.1291 - 1304, 2022-06 |
| SENIN: An energy-efficient sparse neuromorphic system with on-chip learning Choi, Myung-Hoon; Choi, Seungkyu; Sim, Jaehyeong; Kim, Lee-Sup, 22nd IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), IEEE-CAS and ACM-SIGDA, 2017-07-25 |
| Timing error masking by exploiting operand value locality in SIMD architecture = SIMD 구조의 피연산자 값 지역성을 활용한 타이밍 오류 제거 기법link Sim, Jaehyeong; 심재형; et al, 한국과학기술원, 2014 |
| Timing error masking by exploiting operand value locality in SIMD architecture Sim, Jaehyeong; Park, Jun-Seok; Paek, Seung-Wook; Kim, Lee-Sup, 32nd IEEE International Conference on Computer Design, ICCD 2014, pp.90 - 96, IEEE Circuits and Systems Society, 2014-10 |
| TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training Choi, Seungkyu; Sim, Jaehyeong; Kang, Myeonggu; Kim, Lee-Sup, 23rd IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp.104 - 109, ACM/IEEE, 2018-07-24 |
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