Browse "School of Electrical Engineering(전기및전자공학부)" by Author Shin, Young Soo
Showing results 1 to 16 of 16
| Accurate wirelength prediction for placement driven synthesis through machine learning = 배치 기반 합성을 위한 기계학습을 이용한 정확한 배선길이 예측link Fan, Yuepeng; Shin, Young Soo; et al, 한국과학기술원, 2018 |
| Automatic clock gating synthesis of gate-level netlist = 게이트 레벨 넷리스트의 클럭 게이팅 자동 합성link Han, Inhak; 한인학; et al, 한국과학기술원, 2017 |
| Buffer insertion to remove hold violations at multiple process corners Han, In Hak; Hyun, Dai Joon; Shin, Young Soo, 21st Asia and South Pacific Design Automation Conference, pp.232 - 237, IEEE, ACM, 2016-01-26 |
| Calibration of interconnect corners using on-chip ring oscillators Hyun, Dai Joon; Shin, Young Soo, 12th International SoC Design Conference, pp.141 - 142, 대한전자공학회, IEEE, 2015-11-04 |
| Cut redistribution for MP-DSAL with consideration of GP density = GP 밀도를 고려한 다중 패터닝 직접 자기조립용 컷 재배치link Ponghiran, Wachirawit; Shin, Young Soo; et al, 한국과학기술원, 2017 |
| Electrothermal analysis with generalized boundary conditions Choi, Su Hyeong; Shim, Seong Bo; Shin, Young Soo, 12th International SoC Design Conference, pp.39 - 40, 대한전자공학회, IEEE, 2015-11-03 |
| Etch proximity correction through machine-learning-driven etch bias model Shim, Seong Bo; Shin, Young Soo, SPIE Advanced Lithography, SPIE, 2016-02-23 |
| Integrated routing and fill for self-aligned double patterning (SADP) using grid-based design Song, Young Soo; Lee, Jee Myung; Shin, Young Soo, SPIE Advanced Lithography, SPIE, 2016-02-24 |
| Lithography test pattern synthesis and PVB prediction using GANs = GAN을 이용한 리소그래피 테스트 패턴 합성과 PVB 예측link Kareem, Pervaiz; Shin, Young Soo; et al, 한국과학기술원, 2021 |
| Machine learning (ML)-guided OPC using basis functions of polar Fourier transform Shim, Seongbo; Choi, Su Hyeong; Shin, Young Soo, SPIE Advanced Lithography, SPIE, 2016-02-24 |
| Mask optimization for directed self-assembly lithography: inverse DSA and inverse lithography Shin, Young Soo; Shim, Seong Bo, 21st Asia and South Pacific Design Automation Conference, pp.83 - 88, IEEE, ACM, 2016-01-26 |
| Modeling interconnect corners under double patterning misalignment Hyun, Dai Joon; Shin, Young Soo, SPIE Advanced Lithography, SPIE, 2016-02-24 |
| Physical design and mask optimization for directed self-assembly lithography (DSAL) Shim, Seong Bo; Shin, Young Soo, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , pp.80 - 85, IEEE, IFIP, 2015-10-06 |
| Physical synthesis of DNA circuits with spatially localized gates = 로컬 DNA 게이트를 이용한 DNA 회로 합성 기법link Oh, Jeong-hun; 오정훈; et al, 한국과학기술원, 2015 |
| Physical synthesis of DNA circuits with spatially localized gates Jung, Jin Wook; Hyun, Dai Joon; Shin, Young Soo, The 33rd IEEE International Conference on Computer Design , pp.280 - 286, IEEE Circuits and Systems Society, 2015-10-20 |
| Redundant via insertion in directed self-assembly lithography Shim, Seong Bo; Chung, Woo Hyun; Shin, Young Soo, Design, Automation & Test in Europe (DATE), pp.55 - 60, European Design and Automation Association (EDAA), 2016-03-15 |
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