Browse "School of Electrical Engineering(전기및전자공학부)" by Author Paik, S
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| HLS-l: High-level synthesis of high performance latch-based circuits Paik, S; Shin, I; Shin, Youngsoo, 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, pp.1112 - 1117, 2009-04-20 |
| Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power Paik, S; Nam, GJ; Shin, Youngsoo, International Conference on Computer-Aided Design (ICCAD), pp.640 - 646, IEEE/ACM, 2011-11-09 |
| Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits Lee, H; Paik, S; Shin, Youngsoo, 2008 International Conference on Computer-Aided Design, ICCAD, pp.224 - 229, ACM SIGDA and IEEE CEDA, 2008-11-10 |
| Register allocation for high-level synthesis using dual supply voltages Shin, I; Paik, S; Shin, Youngsoo, 2009 46th ACM/IEEE Design Automation Conference, DAC 2009, pp.937 - 942, ACM Special Interest Group on Design Automation (SIGDA), 2009-07-26 |
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