Browse "School of Electrical Engineering(전기및전자공학부)" by Author 1255

Showing results 1 to 60 of 82

1
3-D thermal simulation with dynamic power profiles

Choi, E.; Shin, Youngsooresearcher, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp.2765 - 2768, 2008-05-18

2
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost

Bhattacharya, S; Darringer, J; Ostapko, D; Shin, Youngsooresearcher, Sixth International Symposium on Quality Electronic Design, pp.482 - 487, IEEE, 2005-03

3
A pipeline architecture with 1-cycle timing error correction for low voltage operations

Insup Shin; Jae-Joon Kim; Jae-Joon Kim; Shin, Youngsooresearcher, International Symposium on Low Power Electronics and Design, pp.199 - 204, International Symposium on Low Power Electronics and Design, 2013-09-05

4
Active mode 파워 게이팅 회로의 physical design

서문준; 신인섭; 신영수researcher, 한국반도체학술대회, 한국반도체학회, 2011-02-17

5
An efficient computer-aided prototyping system based on FPGAs

Kim, Y; Shin, Youngsooresearcher; Kim, K; Won, J; Choi, K, 대한전자공학회 추계종합학술대회, pp.1382 - 1385, 대한전자공학회, 1995

6
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping

Kim, Y; Kim, K; Shin, Youngsooresearcher; Ahn, T; Sung, W; Choi, K, Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), pp.101 - 106, ACM Press, 1995-08

7
An Integrated Hardware-Software Cosimulation Environment with Automated Interface Generation

Kim, K; Kim, Y; Shin, Youngsooresearcher; Choi, K, IEEE Int'l Workshop on Rapid Systems Prototyping, pp.66 - 71, IEEE, 1996-06

8
Analysis and minimization of short-circuit current in mesh clock network

Seongbo Shim; Minyoung Mo; Sangmin Kim; Shin, Youngsooresearcher, International Conference on Computer Design, pp.459 - 462, International Conference on Computer Design, 2013-10-08

9
Analysis and optimization of gate leakage current of power gating circuits

Kim, H.-O.; Shin, Youngsooresearcher, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, pp.565 - 569, IEEE, 2006-01-24

10
Analysis of power consumption in VLSI global interconnects

Shin, Youngsooresearcher; Kim, H.-O., IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.4713 - 4716, IEEE, 2005-05-23

11
Architecting voltage islands in core-based System-on-a-Chip designs

Hu, J; Shin, Youngsooresearcher; Dhanwada, N; Marculescu, R, Int'l Symp. on Low Power Electronics and Design (ISLPED), pp.180 - 185, ACM Press, 2004-08

12
Area efficient neuromorphic circuit based on stochastic computation

Yoon, Kiwon; Choi, Suhyeong; Shin, Youngsooresearcher, International SoC Design Conference, IEEE, IEIE, 2016-10-23

13
Bounded potential slack: Enabling time budgeting for dual-Vt allocation of hierarchical design

Seomun, J.; Paik, S.; Shin, Youngsooresearcher, 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, pp.581 - 586, ASP-DAC 2010, 2010-01-18

14
Clock gating: design or synthesis?

신영수researcher, 한국반도체학술대회, 한국반도체학회, 2012-02

15
Clustering-based clock network synthesis of pulsed-latch circuits

Shin, Youngsooresearcher, Design Automation Conf. (DAC), Design Automation Conf. (DAC), 2011

16
Compact thermal models: assessment and pitfalls

Jung, J; Shin, Youngsooresearcher, 2011 International SoC Design Conference (ISOCC), pp.337 - 340, IEEE, 2011-11-18

17
Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems

Shin, Youngsooresearcher; Kawaguchi, H; Sakurai, T, Custom Integrated Circuits Conf. (CICC), pp.553 - 556, IEEE, 2001-05

18
Coupling-driven bus design for low-power application-specific systems

Shin, Youngsooresearcher; Sakurai, T, Design Automation Conf. (DAC), pp.750 - 753, ACM Press, 2001-06

19
Defect probability of directed self-assembly lithography: fast identification and post-placement optimization

Shim, Seongbo; Chung, Woo Hyun; Shin, Youngsooresearcher, 2015 International Conference On Computer Aided Design, pp.404 - 409, ACM SIGDA and IEEE CEDA, 2015-11-03

20
Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification

Kim, Y; Shin, Youngsooresearcher; Kim, K; Won, J; Choi, K, 1995 IEEE International Symposium on Circuits and Systems, pp.924 - 927, IEEE, 1995-04

21
Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign

Shin, Youngsooresearcher; Choi, K, 5th International Workshop on Hardware/Software Codesign, pp.3 - 7, IEEE, 1997-03

22
Enhancing Schedulability of Hard Real-Time Systems through Codesign

Shin, Youngsooresearcher; Choi, K, IEEE International Symposium on Circuits and Systems, pp.1576 - 1579, IEEE, 1997-06

23
Estimation of power distribution in VLSI interconnects

Shin, Youngsooresearcher; Sakurai, T, International Symposium on Low Power Electronics and Design, pp.370 - 375, IEEE, 2001-08

24
Experimental evaluation of cooperative voltage scaling (CVS): a case study

Kawaguchi, H; Shin, Youngsooresearcher; Sakurai, T, IEEE Workshop on Power Management for Real-Time and Embedded Systems, pp.17 - 23, IEEE, 2001-05

25
Exploring the Opportunity of Optimizing Sequencing Elements in ASIC Designs

Paik, Seungwhun; Kung, Jaeha; Shin, Youngsooresearcher, The 54th IEEE Ineternational Midwest Symposium on Circuits and Systems (MWSCAS), pp.394 - 397, IEEE, 2011-08-09

26
Fast Monte Carlo method via reduced sample number and node filtering

Han, I.; Yu, L.-E.; Shin, Youngsooresearcher, 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010, pp.126 - 129, IEEE, 2010-06-02

27
Fine-grain control of multiple functional blocks with lookup table-based adaptive body biasing

Choi, B; Shin, Youngsooresearcher, Int'l SoC Design Conf. (ISOCC), IEEE, 2006-10

28
Folded Circuit Synthesis: Logic Simplification Using Dual Edge-Triggered Flip-Flops

Han, Inhak; Shin, Youngsooresearcher, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), pp.17 - 20, IEEE, 2013-05-30

29
Frequency and yield optimization using power gates in power-constrained designs

Nam, S.K.; Jun, S.; Sinkar, A.; Jungseob, L.; Tae, H.H.; Ken, C.; Shin, Youngsooresearcher, 2009 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'09, pp.121 - 126, 2009-08-19

30
Gate Delay Modeling for Static Timing Analysis of Body-Biased Circuits

Baek, Donkyu; Ship, Insup; Shin, Youngsooresearcher, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), IEEE, 2012-05-31

31
Hierarchical temporal memory 방식을 이용한 뇌 인지 기능 모사

신영수researcher, 한국반도체학술대회, 한국반도체학회, 2012-02

32
HLS-l: High-level synthesis of high performance latch-based circuits

Paik, S; Shin, I; Shin, Youngsooresearcher, 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, pp.1112 - 1117, 2009-04-20

33
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

Paik, S; Nam, GJ; Shin, Youngsooresearcher, International Conference on Computer-Aided Design (ICCAD), pp.640 - 646, IEEE/ACM, 2011-11-09

34
Leakage control through fine-grained power gating: methodology and implementation

Knebel, D; Kosonocky, S; Bhattacharya, S; Puri, R; Shin, Youngsooresearcher, IBM Austin Conference on Energy-Efficient Design (ACEED), IBM, 2004

35
Leakage-Aware Technology Mapping for Sequential Circuits

허세완; 신영수researcher, 제 14회 한국반도체학술대회, 2007-02-08

36
Localized DNA circuit design with majority gates

Jung, Jinwook; Shin, Youngsooresearcher, IEEE BioMedical Circuits and Systems Conference (BioCAS), pp.172 - 175, IEEE, 2016-10-17

37
Long-Term Power Minimization of Dual-Vt CMOS Circuits

Kim, S; Shin, Youngsooresearcher; Kosonocky, S; Hwang, W., Int'l ASIC/SOC Conf., pp.323 - 327, IEEE, 2002-09

38
Machine learning (ML)-based lithography optimizations

Shin, Youngsooresearcher; Shim, Seongbo; Choi, Suhyeong, IEEE Asia Pacific Conference on Circuits and Systems, IEEE, 2016-10-25

39
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops

Kim, J.; Shin, Youngsooresearcher, 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, pp.797 - 802, 2007-11-04

40
Modeling and analysis of power for System-on-a-Chip design

Nair, I.I.; Shin, Youngsooresearcher; Bergamaschi, R.A.; Bhattacharya, S; Darringer, J; Kosonocky, S, IBM Austin Conference on Energy-Efficient Design (ACEED), IBM, 2003-03

41
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements

Paik, S.; Shin, Youngsooresearcher, 45th Design Automation Conference, DAC, pp.600 - 605, 2008-06-08

42
Narrow bus encoding for low power systems

Shin, Youngsooresearcher; Choi, K, Asia South Pacific Design Automation Conf. (ASPDAC), pp.217 - 220, ACM Press, 2000-01

43
Partial bus-invert coding for power optimization of system level bus

Shin, Youngsooresearcher; Chae, SI; Choi, K, Symp. on Low Power Electronics and Design (ISLPED), pp.127 - 129, ACM Press, 1998-08

44
Physical design methodology for power gating circuits with transparent use of standard cells

김형옥; 신영수researcher, 한국반도체학술대회, pp.877 - 878, 2006

45
Physical design methodology of power gating circuits for standard-cell-based design

Kim, HO; Shin, Youngsooresearcher; Kim, H; Eo, I, Design Automation Conf. (DAC), pp.109 - 112, IEEE/ACM, 2006-07

46
Placement optimization for MP-DSAL compliant layout

Shim, Seongbo; Chung, Woohyun; Shin, Youngsooresearcher, IEEE International Conference on IC Design and Technology (ICICDT), IEEE/ACM, 2016-06-27

47
Power conscious fixed priority scheduling for hard real-time systems

Shin, Youngsooresearcher; Choi, K, Design Automation Conf. (DAC), pp.134 - 139, 1999-06

48
Power gating and supply control for low standby leakage power of VLSI circuits

Heo, S; Kim, HO; Shin, Youngsooresearcher, Symposium on Low-Power and High-Speed Chips (COOL Chips), pp.305 - 307, IEEE, 2006-04

49
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors

Shin, Youngsooresearcher; Choi, K; Sakurai, T, IEEE/ACM International Conference on Computer Aided Design, pp.365 - 368, IEEE, 2000-11

50
Power-Aware slack distribution for hierarchical vlsi design

Kim, H.O.; Shin, Youngsooresearcher, IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.4150 - 4153, IEEE, 2005-05-23

51
Power-gating-aware high-level synthesis

Choi, E.; Shin, C.; Kim, T.; Shin, Youngsooresearcher, ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, pp.39 - 44, 2008-08-11

52
Pulsed-latch ASIC Synthesis in Industrial Design Flow

Kim, Sangmin; Kim, Duckhwan; Shin, Youngsooresearcher, Asia and South Pacific Design Automation Conference, pp.356 - 361, IEEE, 2013-01

53
Pulsed-latch aware placement for timing-integrity optimization

Chuang, Y.-L.; Kim, S.; Shin, Youngsooresearcher; Chang, Y.-W., 47th Design Automation Conference, DAC '10, pp.280 - 285, DAC '10, 2010-06-13

54
Pulsed-latch circuits to push the envelope of ASIC design

Paik, S.; Shin, Youngsooresearcher, 2010 International SoC Design Conference, ISOCC 2010, pp.150 - 153, ISOCC 2010, 2010-11-22

55
Pulser gating: A clock gating of pulsed-latch circuits

Kim, S.; Han, I.; Paik, S.; Shin, Youngsooresearcher, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, pp.190 - 195, ASP-DAC 2011, 2011-01-25

56
Rate assignment for embedded reactive real-time systems

Shin, Youngsooresearcher; Choi, K, Euromicro Workshop on Digital Systems Design, pp.237 - 242, 1998

57
Register grouping for synthesis of clock gating logic

Han, In-Hak; Kim, Jongkyou; Yi, Junhwan; Shin, Youngsooresearcher, IEEE International Conference on IC Design and Technology (ICICDT), IEEE/ACM, 2016-06-27

58
Schedulability-driven performance analysis of multiple mode embedded real-time systems

Shin, Youngsooresearcher; Kim, D; Choi, K, Design Automation Conf. (DAC), pp.495 - 500, ACM Press, 2000-06

59
SEAS: a system for early analysis of SoCs

Bergamaschi, R.A.; Shin, Youngsooresearcher; Dhanwada, N; Bhattacharya, S; Dougherty, W.E.; Nair, I.I.; Darringer, J; et al, Int'l Conf. on Hardware/Software Codesign and System Synthesis, pp.150 - 155, ACM Press, 2003-10

60
Selectively patterned masks: Beyond structured ASIC

Baek, D.; Shin, I.; Paik, S.; Shin, Youngsooresearcher, 2010 International SoC Design Conference, ISOCC 2010, pp.154 - 157, ISOCC 2010, 2010-11-22

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