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1
Design of pipelined cache DRAM for fast random-access = 고속 Random-access를 위한 pipelined cache DRAM의 설계link

Kook, Jeong-Hoon; 국정훈; et al, 한국과학기술원, 2001

2
POPeye: A Simulator for a DRAM Performance Enaluator

유회준; 이강민; 윤치원; 우람찬; 국정훈, 한국 반도체 학술대회, 2001

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