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Showing results 1 to 4 of 4

1
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M

Hwang, Chanwoong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2841 - 2855, 2022-09

2
A Low-jitter Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction

Hwang, Chan woong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk, IDEC Journal of Integrated Circuits and Systems, v.9, no.4, pp.37 - 43, 2023-10

3
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.12, pp.3527 - 3537, 2022-12

4
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68

Park, Suneui; Yoo, Seyeon; Shin, Yuhwan; Lee, Jeonghyun; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.1, pp.78 - 89, 2023-01

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