Browse "School of Electrical Engineering(전기및전자공학부)" by Author Yu, C.-H.
Showing results 1 to 14 of 14
| A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2006 IEEE International Solid-State Circuits Conference, ISSCC, 2006-02-06 |
| A 186Mvertices/s 161mW floating-point vertex processor for mobile graphics systems Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2007 IEEE Custom Integrated Circuits Conference, CICC, pp.579 - 582, 2007-09-16 |
| A 33.2Mvertices/sec programmable geometry engine for multimedia embedded systems Yu, C.-H.; Kim, D.; Kim, Lee-Sup, IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.4574 - 4577, IEEE, 2005-05-23 |
| A 36fps SXGA 3D display processor with a programmable 3D graphics rendering engine Kim, S.-H.; Yoon, J.-S.; Yu, C.-H.; Kim, D.; Chung, K.; Lim, H.S.; Park, HyunWook; et al, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, pp.276 - 277, IEEE, 2007-02-11 |
| A 3D graphics processor with fast 4D vector inner product units and power aware texture cache Yoon, J.-S.; Kim, D.; Yu, C.-H.; Kim, Lee-Sup, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.539 - 542, 2008-09-21 |
| A hardware-like high-level language based environment for 3D graphics architecture exploration Lee, I.; Kim, J.-Y.; Im, Y.-H.; Choi, Y.; Shin, H.; Han, C.; Kim, D.; et al, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, IEEE, 2003-05-25 |
| A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter Yu, C.-H.; Kim, Lee-Sup, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, IEEE, 2003-05-25 |
| A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics Chung, K.; Yu, C.-H.; K, D; Kim, Lee-Sup, 2008 International SoC Design Conference, ISOCC 2008, 2008-11-24 |
| An adaptive spatial filter for early depth test Yu, C.-H.; Kim, Lee-Sup, 2004 IEEE International Symposium on Cirquits and Systems - Proceedings, IEEE, 2004-05-23 |
| An efficient texture cache for programmable vertex shaders Cho, S.; Yu, C.-H.; Kim, Lee-Sup, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.3834 - 3837, IEEE, 2006-05-21 |
| An SoC with 1.3Gtexels/s 3D graphics full pipeline engine for consumer applications Kim, D.; Chung, K.; Yu, C.-H.; Kim, C.-H.; Lee, I.; Bae, J.; Kim, Y.-J.; et al, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.144 -, IEEE, 2005-02-06 |
| Tessellation-enabled shader for a bandwidth-limited 3D graphics engine Chung, K.; Yu, C.-H.; Kim, D.; Kim, Lee-Sup, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.367 - 370, 2008-09-21 |
| Triangle-level depth filter method for bandwidth reduction in 3D graphics hardware Yoon, J.-S.; Yu, C.-H.; Kim, D.; Kim, Lee-Sup, 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, pp.765 - 768, 2007-05-27 |
| Vertex cache of programmable geometry processor for mobile multimedia application Chung, K.; Yu, C.-H.; Kim, Lee-Sup, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.1908 - 1911, IEEE, 2006-05-21 |
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