Browse "School of Electrical Engineering(전기및전자공학부)" by Author Kwon, Young-Su
Showing results 1 to 8 of 8
| Fast Priority Balancing Circuit Partitioning for Multiple FPGAs using Time-multiplexed, Multicasting Interconnection Kyung, Chong-Min; Kwon, Young-Su, 2003 SoC Design Conference(SDC), pp.412 - 416, 2003 |
| FGA : Geometry Acceleration System with VLIW Processor in 3D Graphics Kyung, Chong-Min; Kwon, Young-Su; Lee, Jun-Hee; Im, Yeon-Ho; Byun, Sung-Jae; Jeon, Young-Wook; Nam, Sang-Joon; et al, COOL Chips III, pp.261 - 270, 2000-04 |
| Floating-point geometry processing unit for 3D graphics acceleration = 3차원 그래픽스를 위한 부동 소수점 기하 연산기 설계link Kwon, Young-Su; 권영수; et al, 한국과학기술원, 1999 |
| FLOVA: a four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit Nam, Sang-Joon; Kim, Byoung-Woon; Im, Yeon-Ho; Kwon, Young-Su; Lee, Jun-Hee; Cheon, Young-Wook; Byun, Sung-Jae; et al, CICC 2000: 22nd Annual Custom Integrated Circuits Conference, pp.551 - 554, CICC, 2000-05-21 |
| Performance-driven design partitioning and synchronization for multi-FPGA simulation accelerator = 다중 재설정 가능 칩을 이용한 시뮬레이션 가속기의 성능 향상을 위한 디자인 분할과 동기화 알고리즘link Kwon, Young-Su; 권영수; et al, 한국과학기술원, 2004 |
| Performance-Driven Event-Based Design Mapping in Multi-FPGA Simulation Accelerator Kyung, Chong-Min; Kwon, Young-Su; Lee, Jae-Gon, International SoC Design Conference(ISOCC) 2004, pp.218 - 221, 2004-10 |
| Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection Kyung, Chong-Min; Kwon, Young-Su; Yang, Woo-Seung, IFIP International Conference on Very Large Scale Integration(IFIP VLSI-SOC 2003), pp.123 - 128, 2003-12 |
| Simulation Acceleration of Transaction-Level Models for SoC with RTL sub-blocks Kyung, Chong-Min; Lee, Jae-Gon; Yang, Wooseung; Kwon, Young-Su; Kim, Young-Il, ASP-DAC'2005, 2005 |
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