Browse "School of Electrical Engineering(전기및전자공학부)" by Author Cho, Sang-Hyun
Showing results 1 to 6 of 6
| A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs Hwang, Sun-Il; Chung, Jaehyun; Kim, Hyeon-June; Jang, Il Hoon; Seo, Min-Jae; Cho, Sang-Hyun; Kang, Heewon; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.3, pp.1119 - 1126, 2018-03 |
| A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling Jang, Il Hoon; Seo, Min-Jae; Cho, Sang-Hyun; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sunwoo; Choi, Michael; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1139 - 1148, 2018-04 |
| A 550-mu W 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction Cho, Sang-Hyun; Lee, Chang-Kyo; Kwon, Jong-Kee; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.46, pp.1881 - 1892, 2011-08 |
| A Power Efficient Conversion Techique for SAR ADC Ryu, Seung-Tak; Cho, Sang-Hyun, TriSAI, pp.307 - 309, 2009 |
| A Reference-Driver Free ADC Architecture Ryu, Seung-Tak; Lee, Chang-Kyo; Cho, Sang-Hyun, TriSAI, pp.304 - 306, 2009 |
| A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm Cho, Sang-Hyun; Lee, Chang-Kyo; Lee, Sang-Gug; Ryu, Seung-Tak, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.4, pp.765 - 769, 2012-04 |
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