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A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS Park, Y.-H.; Han, S.-H.; Kim, J.-S.; Lee, S.-J.; Kook, J.-H.; Lim, J.-W.; Woo, R.; et al, 2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC, pp.242 - 243, 2000-02-07 |
Design and implementation of CMOS LVDS 2.5Gb/s transmitter and 1.3Gb/s receiver for optical interconnections Lee, J.; Lim, J.-W.; Song, S.-J.; Song, S.-S.; Lee, W.-J.; Yoo, Hoi-Jun, Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications, v.626, 2000-04-24 |
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