Showing results 1 to 3 of 3
A Fast Synchronous Pipelined DRAM(SP-DRAM) Architecture with SRAM Buffers Yoo, Hoi-Jun; Yoon, Chi-Woen; Im, Yon-Kyun; Han, Seon-Ho; Jung, Tae-Sung, International Conference on VLSI and CAD, pp.285 - 288, 1999 |
A VPM Architecture for a Fast Row-Cycle DRAM Yoo, Hoi-Jun; Yoon, Chi-Woen; Im, Yon-Kyun; Han, Seon-Ho; Jung, Tae-Sung, IEEE Asia Pacific Conference on ASICs, pp.388 - 391, 1999 |
POPeye:A System Analysis Tool for DRAM Performance Measurement Yoo, Hoi-Jun; Im, Yon-Kyun; Yoon, Chiwoen; Jung, Tae-Sung, International Conference on VLSI and CAD, pp.590 - 592, 1999 |
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