Showing results 7 to 10 of 10
SoC design environment with automated configurable bus generation for rapid prototyping Lee, S.-H.; Lee, J.-G.; Kim, S.; Hwangbo W.; Kyung, Chong-Min, ASICON 2005: 2005 6th International Conference on ASIC, v.1, pp.122 - 125, 2005-10-24 |
Stability analysis of switched systems with impulse effects Lee, S.-H.; Lim, Jong-Tae, Proceedings of the 1999 IEEE International Symposium on Intelligent Control - Intelligent Systems and Semiotics, pp.79 - 83, 1999-09-15 |
System-level HW/SW Co-simulation framework for multiprocessor and multithread SoC Chung, M.-K.; Yang, S.; Lee, S.-H.; Kyung, Chong-Min, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), v.2005, pp.177 - 180, 2005-04-27 |
The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Sil-xGex/Si p-MOSFETs with high-K/metal gate Loh, W.-Y.; Majhi, P.; Lee, S.-H.; Oh, J.-W.; Sassman, B.; Young, C.; Bersuker, G.; et al, 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT, pp.56 - 57, 2008-06-17 |
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