Browse "School of Electrical Engineering(전기및전자공학부)" by Author 237
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| C-based RTL design verification methodology for complex microprocessor Yim, JS; Hwang, YH; Park, CJ; Choi, H; Yang, WS; Oh, HS; Park, In-Cheol; et al, Proceedings of the 1997 34th Design Automation Conference, pp.83 - 88, 1997-06-09 |
| CAD for Microsystems Design Kyung, Chong-Min, KUSDAM, 1993-11 |
| CAD Software 개발에 관한 연구 경종민; 박송배; 임인철; 차균현; 김형곤, 과학기술처 '86 특정연구결과 발표회, pp.69 - 72, 1987 |
| CBLO: A clustering based linear ordering for netlist partitioning Seong, Kwang-Su; Kyung, Chong-Min, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.43 - 48, 1997-01-28 |
| CCP와 시뮬레이티드 어닐링을 이용한 회로 배치 경종민; 박인철, 씨에이디연구회 합동학술발표회, v.6, no.1, pp.215 - 218, 1988년도 반도체 재료및 부품연구회, 1988 |
| Channel routine Using 0-1 Quadratic Integer Programming Kyung, Chong-Min; Lee, P.H., JTC-CSCC, 1992-07 |
| Characterization of Two-Dimensional Impurity Profile in Semiconductor Using Direct Solution Method Kyung, Chong-Min; Yang, Y.Y.; Oh, H.C., 1984 International Electronic Devices and Materials Symposium, pp.213 - 218, 1984-09 |
| Charge-Coupled A/D Converter Kim, Choong Ki; Kyung, Chong-Min, IEEE Custom Integrated Circuits Conference, pp.94 - 98, 1981-05 |
| Circuit Placement in arbitrary-Shaped Region Using Self-Organization Kyung, Chong-Min; Kim, S.S., International Symposium on Circuits and Systems, 1989-05 |
| Circuit Placement in Rectilinear Region Using Simulated Annealing and Self-Organization Park, In-Cheol; Kyung, Chong-Min, 1988 International Computer Symposium, 1988-12 |
| Circuit Placement Using CCP and Simulated Annealing 박인철; 경종민, Conference on Semiconductors, Materials, Components and CAD, pp.215 - 218, 1988 |
| CMOS Cell Library를 이용한 Sort Processor Chip의 설계 경종민; 홍윤식; 정태성; 윤병진; 양영일; 어길수; 박규호; et al, 대한전자공학회 하계종합학술대회 , v.7, no.1, pp.84 - 87, 1984 |
| CMOS Latch-Up 현상의 실험적 해석 경종민; 고요한; 김충기, 대한전자공학회 CAD, 반도체, 재료 및 부품연구회 합동학술발표회, pp.85 - 87, 대한전자공학회, 1985 |
| CMOS Polycell 의 자동생성 경종민; 김한흥, 대한전자공학회 추계종합학술대회, pp.424 - 426, 대한전자공학회, 1985 |
| Co-Development of Media Processor and Source-level Debugger Using Hardware Emulation Kyung, Chong-Min; Kim, B.W.; Kang, K.G.; Nam, S.J.; Im, Y.H.; Chang, S.I., International Conference on Signal Processing Application and Technology(ICSPAT), 1999-11 |
| Co-development of Media-processor and Source-level Debugger using Emulation-based Validation Kyung, Chong-Min; Im, Y.H.; Nam, S.J.; Kim, B.W.; Kang, K.G.; Lee, D.H.; Yang, J.H.; et al, International Conference on VLSI and CAD(ICVC'99), pp.95 - 98, 1999-10 |
| Code Generation for Embedded Processors with Complex Instructions Lee, J.Y.; Yoon, H.D.; Park, In-Cheol; Yang, J.H.; Kyung, Chong-Min, International Conference on VLSI and CAD(ICVC'99), pp.525 - 528, 1999-10 |
| Communication-efficient hardware acceleration for fast functional simulation Kim, Y.-I.; Yang, W.; Kwon, Y.-S.; Kyung, Chong-Min, Proceedings of the 41st Design Automation Conference, pp.293 - 298, 2004-06-07 |
| Concurrent Design Methodology for GRIMDOL Microprocessor System Kyung, Chong-Min, International Conference on VLSI and CAD, 1993-11 |
| Conforming Inverted Data Store for Low Power Memory Kyung, Chong-Min; Chang, Y.S.; Park, B.I., International Symposium on Low Power Electronics and Design(ISLPED'99), pp.91 - 93, 1999-08 |
| Content Switching Network Processor and Scalable Switch Fabric for Gigabit Ethernet(Best Paper Award-Samsung) Kyung, Chong-Min; Chang, You-Sung; Yi, Ju-Hwan; Oh, Hun-Seung; Lee, Seung-Wang; Kang, Moo-Kyung; Chun, Jung-Bum; et al, 2003 SoC Design Conference(SDC), pp.854 - 859, 2003 |
| Current Status and Challenges of SoC Verification for Embedded Systems Market Kyung, Chong-Min; Yang, Wooseung; Chung, Moo-Kyeong, IEEE International SOC Conference, pp.213 - 216, 2003-09 |
| Customization of a CISC processor core for low-power applications Chang, Y.S.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, ICCD'99(International Conference on Computer Design), pp.152 - 157, 1999-10 |
| Cycle-Accurate Co-Emulation with SystemC Kyung, Chong-Min; Ki, Ando; Park, Bong-Il; Lee, Jae-Gon, 2003 SoC Design Conference(SDC), pp.688 - 691, 2003 |
| Cycle-accurate verification of AHB-based RTL IP with transaction-level system environment Shim, H.; Lee, S.-H.; Woo, Y.-S.; Chung, M.-K.; Lee, J.-G.; Kyung, Chong-Min, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, pp.135 - 138, 2007-04-26 |
| Design and management of 3D-stacked NUCA cache for chip multiprocessors Jung, J.; Kang, K.; Kyung, Chong-Min, 21st Great Lakes Symposium on VLSI, GLSVLSI 2011, pp.91 - 96, ACM, 2011-05-02 |
| Design of energy-aware video codec-based system Na, S.; Kim, J.; Kim, J.; Kim, G.; Kyung, Chong-Min, 1st International Conference on Green Circuits and Systems, ICGCS 2010, pp.201 - 206, 1st International Conference on Green Circuits and Systems, ICGCS 2010, 2010-06-21 |
| Design Rule Check for Integrated Circuit Using PC Park, In-Cheol; Eo, K.S.; Kyung, Chong-Min, KITE Electronics Eng. Symposium, pp.1547 - 1550, 1987 |
| Design Rule Check program의 개발 경종민; 어길수; 김경태, 대한전자공학회 하계종합학술대회, v.7, no.1, pp.88 - 90, 대한전자공학회, 1984 |
| Design verification of complex microprocessors Yim, J; Park, C; Yang, W; Oh, H; Choi, H; Lee, S; Won, N; et al, Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems, pp.441 - 448, 1996-11-18 |
| Diffusion--An analytic procedure applied to macro cell placement Kyung, Chong-Min; Kraus, Peter V.; Mlynski, Dieter A., 1990 IEEE International Conference on Computer-Aided Design - ICCAD-90, pp.102 - 105, 1990-11-11 |
| DIVA:Dual-Issue VLIW Architecture with Media Instructions for Image Processing Nam, S.J.; Kwon, Y.S.; Park, In-Cheol; Kyung, Chong-Min, 대한전자공학회 CAD 및 VLSI 설계연구회 학술발표회, pp.117 - 122, 대한전자공학회, 1999 |
| DVFS algorithm exploiting correlation in runtime distribution Kyung, Chong-Min; Kim, Jungsoo; Yoo, Sungjoo, 제16회 한국반도체학술대회(KCS), 2009 |
| Early in-system verification of behavioral chip models Park, C.J.; Lee, S.J.; Park, B.I.; Choi, H.; Lee, J.G.; Kim, Y.I.; Park, In-Cheol; et al, High-level Design Validation and Test Workshop 1999, pp.61 - 65, 1999-09 |
| EDGE PAINTING MACHINE: A HARDWARE FOR IMAGE RASTERIZATION Kim, Sung Soo; Eo, Kil Su; Kyung, Chong-Min, TENCON 87: 1987 IEEE Region 10 Conference, 'Computers and Communications Technology Toward 2000, pp.115 - 119, 1987-08 |
| Efficient State Encoding Algorithm on Hypercube construction Park, S.S.; Hwang, S.H.; Kyung, Chong-Min, IEE ProcEEDINGS OF Computers and Digital TECH, v.142, no.3, pp.225 - 232, IEEE, 1993-11 |
| Energy Minimization of 3D Cache-Stacked Processor Based on Thin-Film Thermoelectric Coolers Kyung, Chong-Min; Rho, Soojung; kang, KyungsU, The 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011-08-08 |
| Energy-aware instruction-set customization for real-time embedded multiprocessor systems Jung, Seungrok; Kim, Jungsoo; Na, Sangkwon; Kyung, Chong-Min, ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'09, pp.335 - 338, 2009-08-19 |
| ESEU--A hardware architecture for fast image generation Bang, Kyung-Il; Bae, Seong-Ok; Kyung, Chong-Min, 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4), v.1, pp.73 - 76, 1990-05-01 |
| Exploiting Intellectural Properities in ASIP Designs for Embedded DSP Software Choi, H.; Yi, J.H.; Lee, J.Y.; Park, In-Cheol; Kyung, Chong-Min, The 36th Design Automation Conference(DAC), pp.939 - 944, 1999-06 |
| Fast and Near Optimal Scheduling in Automatic Data Path Synthesis Park, In-Cheol; Kyung, Chong-Min, 28th ACM/IEEE Design Automation Conference , pp.680 - 685, ACM, 1991-06 |
| Fast Development of Source-level Debugging System Using Hardware Emulation Kyung, Chong-Min; Nam, S.J.; Lee, J.H.; Kim, B.W.; Im, Y.H.; Kwon, Y.S.; Kang, K.G., ASP-DAC'2000, 2000-01 |
| Fast estimation of software energy consumption using IPI(inter-prefetch interval) energy model Kim, J.; Kang, K.; Shim, H.; Hwangbo, W.; Kyung, Chong-Min, 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC, pp.224 - 229, 2007-10-15 |
| Fast Functional Simulation using Suppressed BDDs Kim, B.W.; Park, In-Cheol; Kyung, Chong-Min, SASIMI'98, pp.96 - 100, 1998-10 |
| Fast heuristics for optimal CMOS functional cell layout generation Kwon, Yong-Joon; Kyung, Chong-Min, 1988 IEEE International Symposium on Circuits and Systems, Proceedings, v.3, pp.2423 - 2426, IEEE, 1998-06 |
| Fast Image Generation Method for Animation Kyung, Chong-Min; Kim, J.H., JTC-CSCC91, 1991-07 |
| Fast Priority Balancing Circuit Partitioning for Multiple FPGAs using Time-multiplexed, Multicasting Interconnection Kyung, Chong-Min; Kwon, Young-Su, 2003 SoC Design Conference(SDC), pp.412 - 416, 2003 |
| FGA : Geometry Acceleration System with VLIW Processor in 3D Graphics Kyung, Chong-Min; Kwon, Young-Su; Lee, Jun-Hee; Im, Yeon-Ho; Byun, Sung-Jae; Jeon, Young-Wook; Nam, Sang-Joon; et al, COOL Chips III, pp.261 - 270, 2000-04 |
| Finding Optimal Module Orientations in Macro Cell Placement Jeong, J.C.; Park, In-Cheol; Kyung, Chong-Min, Joint Technical Confernece on Circuits/Systems, Computers and Communications, pp.605 - 608, 대한전자공학회, 1990 |
| Finding Optimal Module Orientations in Macro Cell Placement Kyung, Chong-Min; Jeong, J.C.; Park, I.C., International Symposium on Circuits and System, 1991-06 |
| FLOVA:A Four0-Issue Media Processor with 3D Geometry Kyung, Chong-Min; Nam, S.J.; Kwon, Y.S.; Kim, B.W.; Im, Y.H.; Kang, K.G., International Conference on Signal Processing Application and Technology(ICSPAT), 1999-11 |
| Functional coverage metric generation from temporal event relation graph Kwon, Y.-S.; Kyung, Chong-Min, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, v.1, pp.670 - 671, 2004-02-16 |
| GEP2C02 : A Network Processor for Real-time Content Switching Kyung, Chong-Min; Chang, You-Sung; Oh, Hun-Seung; Yi, Ju-Hwang; Lee, Jun-Hee; Lee, Seung-Wang; Chun, Jung-Bum, Tenth International Symposium on High Performance Computer Architecture(HPCA-10), 2004-02 |
| Global Placement of Macro Cells using Self-Organization Principle Kyung, Chong-Min; Kim, S.S., International Symposium on Circuits and Systems, 1991-06 |
| Graph-Based Algorithm for Technology Mappint Under Timing Constraints Kyung, Chong-Min; Jeong, J.C., Joint Technical Confernece on Circuits/Systems, Computers and Communications, 1990-12 |
| HALO: An efficient global placement strategy for standard cells Yang, Yeong-Yil; Kyung, Chong-Min, 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4), v.1, pp.448 - 451, 1990-05-01 |
| Hardware Accelerator for Scalable Hangul Font Generation Hwang, G.C.; Lee, Y.T.; Park, In-Cheol; Lee, T. H.; Bae, J.H.; Kyung, Chong-Min, Joint Technical Conference on Citcuits/Systems, Computers and Communications, pp.246 - 250, 대한전자공학회, 1990 |
| HDL Saver Allowing Restrat after Souce Modification Chang, Y.S.; Lee, S.J.; Park, In-Cheol; Kyung, Chong-Min, APCHDL'98, pp.23 - 27, 1998-07 |
| HK386: An x86-compatible 32 bit CISC microprocessor Kang, Y.J.; Park, S.H.; Kim, J.S.; Kim, D.T.; Maeng, S.R.; Cho,i H.; Lee, S.J.; et al, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.661 - 662, 1997-01-28 |
| HW/SW Partitioning for Design of Packet Processors Kyung, Chong-Min; Chun, Jung-Bum, IFIP VLSI-SoC Conference, 2005 |
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