Showing results 37521 to 37540 of 51620
Timed compiled-code simulation of embedded software for performance analysis of SOC design Lee, J.-Y.; Park, In-Cheol, 39th Annual Design Automation Conference, DAC'02, pp.293 - 298, 2002-06-10 |
Timed I/O test sequences for discrete event model verification Hong, Ki-Jung; Kim, Tag-Gon, ARTIFICIAL INTELLIGENCE AND SIMULATION BOOK SERIES: LECTURE NOTES IN COMPUTER SCIENCE, v.3397, pp.275 - 284, 2004 |
Timed Petri Nets를 이용한 Job Shop 시스템의 계층적이고 분산적인 모델링 및 스케줄링 전명근; 변증남, 전자공학회논문지, v.28, no.6, pp.40 - 48, 1991-06 |
Timed petri nets를 이용한 공장 자동화 시스템의 scheduling에 관한 연구 = A study on scheduling for factory automation system using timed petri netslink 전명근; Chun, Myung-Geun; et al, 한국과학기술원, 1989 |
Timed Petri Nets를 이용한 공장 자동화 시스템의 스케쥴링 변증남, 제어계측연구회, 로보틱스 및 자동화연구회 합동학술발표회, pp.65 - 68, 1989 |
Timer-based broadcasting for power-aware routing in power-controlled wireless ad hoc networks Lee, Sun-Ho; Eunjeong Choi; Cho, Dong-Ho, IEEE COMMUNICATIONS LETTERS, v.9, no.3, pp.222 - 224, 2005-03 |
Time–wavelength hybrid optical CDMA system with tunable encoder/decoder using switch and fixed delay-line Min, Seong-sik; Yoo, Hark; Won, Yong Hyub, Optics Communications, Vol.216, No.4-6, pp.335-342, 2003-02-15 |
Timing analysis algorithm for clock gated DETFF based circuits 모민영; 김상민; 신영수, 한국반도체학술대회, 한국반도체학회, 2011-02 |
Timing analysis and optimization of sequential circuits with dual-edge-triggered flip-flops = 듀얼-에지-구동 플립플랍을 이용한 순차 회로의 타이밍 분석과 최적화link Oh, Chung-Ki; 오충기; et al, 한국과학기술원, 2009 |
Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating Oh, C.; Kim, S.; Shin, Youngsoo, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp.59 - 62, 2009-05-18 |
Timing Attacks on Access Privacy in Information Centric Networks and Countermeasures Mohaisen, Aziz; Mekky, Hesham; Zhang, Xinwen; Xie, Haiyong; Kim, Yongdae, IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, v.12, no.6, pp.675 - 687, 2015-11 |
Timing Error Detector for OQPSK Signal Seong, J; Lee, HyuckJae; Kim, M, 62nd Technology Conference (VTC-2005), pp.1926 - 1929, IEEE, 2005-09 |
Timing error masking by exploiting operand value locality in SIMD architecture = SIMD 구조의 피연산자 값 지역성을 활용한 타이밍 오류 제거 기법link Sim, Jaehyeong; 심재형; et al, 한국과학기술원, 2014 |
Timing error masking by exploiting operand value locality in SIMD architecture Sim, Jaehyeong; Park, Jun-Seok; Paek, Seung-Wook; Kim, Lee-Sup, 32nd IEEE International Conference on Computer Design, ICCD 2014, pp.90 - 96, IEEE Circuits and Systems Society, 2014-10 |
Timing Estimation Based on Statistical Change of Symmetric Correlator for OFDM Systems Cho, Yong-Ho; Park, Dong-Jo, IEEE COMMUNICATIONS LETTERS, v.17, no.2, pp.397 - 400, 2013-02 |
Timing evaluation of MAC-layer error control on ARM9-based mobile embedded systems Kim, C; Kang, K; Noh, DK; Ryu, J; Ma, JoongSoo, TELECOMMUNICATION SYSTEMS, v.45, pp.329 - 337, 2010-12 |
Timing extraction from baseband data waveforms = 데이타 파형으로부터의 동기신호 추출link Choi, Yang-Hee; 최양희; et al, 한국과학기술원, 1977 |
Timing optimization in SADP process through wire widening and double via insertion SONG, YOUNGSOO; Jung, Jinwook; HYUN, DAIJOON; Shin, Youngsoo, SPIE Advanced Lithography, SPIE, 2018-02-28 |
Timing recovery for sampling detectors in digital magnetic recording Moon, Jaekyun, International Conference on Communications, pp.0 - 0, 1996-06-26 |
Timing Recovery in Conjunction With Maximum Likelihood Sequence Detection in the Presence of Intersymbol Interference Moon, Jaekyun; Lee, Jaewook, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.55, no.9, pp.2884 - 2897, 2008-10 |
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