Browse "School of Electrical Engineering(전기및전자공학부)" by Type Conference
Showing results 14321 to 14340 of 22776
| PanoNetVLAD: Visual Loop Closure Detection in Continuous Space Represented With Panoramic View Using Multiple Shin, Sungjae; KIM, YEEUN; YU, BYEONGHO; LEE, EUNGCHANG; Seo, Dong-Uk; Myung, Hyun, International Conference on Control, Automation and System (ICCAS 2023), Institute of Control, Robotics and Systems, 2023-10-18 |
| Paradlgm shlft for commerclally vlable OPS/OBS with shared buffer and wavelength converter Rhee, June-Koo Kevin; Kim, J.-H.; Han, J.; Im, J.; Choi J., 2007 Photonics in Switching, PS, pp.117 - 118, IEEE, 2007-08-19 |
| Paralledl Simulation of Hierarchical Modular DEVS Models : A Modified Time Warp Approach Park, Kyu Ho, pp.263 - 285, 1995 |
| Parallel architecture for sphere decoder with runtime constraint Lee J.; Kim H.S.; Park, Sin Chong, 2008 5th IEEE Consumer Communications and Networking Conference, CCNC 2008, pp.181 - 184, 2008-01-10 |
| Parallel data processing based on EDMA to save the processing power of a T-DMB software baseband receiver running on a digital signal processor Lee, M.; Jeong, H.J.; Kim, J.; Young, S.S.; Lee, Hwang Soo; Kim, S.-S., 1st International Conference on Intensive Applications and Services, INTENSIVE 2009, pp.34 - 38, IEEE, 2009-04-20 |
| Parallel Discrete Event Simulation for DEVS Cellular Models using a GPU Seok, M.; Kim, Tag-Gon, 2012 Spring Simulation Multiconference, High Performance Computing Symposium (HPC), Spring Simulation Multiconference, 2012-03 |
| Parallel Evolutionary Optimized Pitching Motion Control for F-16 Aircraft Kim, Jong-Hwan, Congress on Evolutionary Computation, IEEE, 2003-12-01 |
| Parallel execution schemes in a Petri net Chang, Won Ho; Oh, Ha Ryoung; Lee, Kwang-Hyung; Park, Kyu Ho; Kim, Myunghwan, Proceedings of the 1988 International Conference on Parallel Processing, v.1, pp.286 - 290, 1988 |
| Parallel IDMA Architecture Based on Interleaving With Replicated Subpatterns Kong, Byeong Yong; Park, In-Cheol, 2019 IEEE 53rd International Conference on Communications (ICC 2019), IEEE, 2019-05-22 |
| Parallel LDPC Decoder Implementation on GPU Based on Unbalanced Memory Coalescing Moon, Jaekyun; Kang, Soonyoung, IEEE Inernational conference on communications, IEEE, 2012-06-10 |
| Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction Kyung, CM; Chung, Moo-Kyoung; Shim, Heejun, 13th Korean Conference on Semiconductors(KCS'2006. 한국반도체학술대회), pp.129 - 130, 2006 |
| Parallel quantum-inspired genetic algorithm for combinatorial optimization problem Han, K.-H.; Park, K.-H.; Lee, C.-H.; Kim, Jong-Hwan, Congress on Evolutionary Computation 2001, pp.1422 - 1429, IEEE, 2001-05-27 |
| Parallel Simulation of Bounded Petri Nets in Single Processor Kim, Tag-Gon; Kim, Young Chan; Kwon, In Sup, SCSC, SCSC, 1999-07 |
| Parallel unravelling for simulating open quantum systems Sinayskiy, Ilya; Park, Kyungdeok; Rhee, June-Koo Kevin; Petruccione, Francesco, Quantum Techniques in Machine Learning (QTML) 2019, pp.87 - 90, KAIST, 2019-10-23 |
| Parallel VLSI Architectures for a Class of LDPC codes Moon, Jaekyun, IEEE International Symposium on Circuits and Systems, pp.0 - 0, 2005-05-15 |
| Parallel 방식을 이용한 2K/4K/8K-point FFT processor 문상철; 박인철, SOC Design Conference, 2002-10 |
| Parallelized Inverse Dynamics Algorithm for Dynamic Control of a Robot Manipulator Kim, S.D.; Roh, C.L.; Chung, Myung Jin, Proceedings of the IFAC Workshop on Algorithms and Architectures for Real-time Control, pp.49 - 53, 1992-08 |
| Parallelized List Sphere Decoder Architecture with Modified Precomputation Park, Sin Chong, ICWMMN 2006 |
| Parallelized VLSI Architecture for List Sphere Decoder Park, Sin Chong, ICACT2007 |
| Parallelized VLSI architecture of single stack based list sphere decoder Kim H.-S.; Seo S.-H.; Park, Sin Chong, 8th International Conference on Signal Processing, ICSP 2006, v.1, 2006-11-16 |
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