Showing results 3 to 7 of 7
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus Kwon, YS; Kyung, Chong-Min, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.24, pp.1444 - 1456, 2005-09 |
Power analysis of VLSI interconnect with RLC tree models and model reduction Shin, Youngsoo; Lee, J, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.15, no.3, pp.399 - 408, 2006-06 |
Power distribution-analysis of VLSI interconnects using model order reduction Shin, Youngsoo; Sakurai, T, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.21, no.6, pp.739 - 745, 2002-06 |
Security considerations in processor interconnect design = 프로세서 인터커넥트 네트워크에서의 보안문제link Song, Won-Jun; 송원준; et al, 한국과학기술원, 2014 |
Signal Integrity Modeling and Analysis of Large-Scale Memristor Crossbar Array in a High-Speed Neuromorphic System for Deep Neural Network Shin, Taein; Park, Shinyoung; Kim, Seongguk; Kim, Subin; Son, Kyungjune; Park, Hyunwook; Lho, Daehwan; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.11, no.7, pp.1122 - 1136, 2021-07 |
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