Showing results 1 to 5 of 5
A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F(2) cell Kim, JS; Choi, YS; Yoo, Hoi-Jun; Seo, KS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.33, no.7, pp.1096 - 1102, 1998-07 |
A study of pipeline architectures for high-speed synchronous DRAMs Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.32, no.10, pp.1597 - 1603, 1997-10 |
Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks Seol, Hoseok; Kim, Minhye; Kim, Taesoo; Kim, Yongdae; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.70, no.4, pp.539 - 551, 2021-04 |
High speed latchup resistant CMOS data output buffer for submicrometre DRAM application Yoo, Hoi-Jun, ELECTRONICS LETTERS, v.32, no.24, pp.2229 - 2230, 1996-11 |
Method to Achieve the Morphotropic Phase Boundary in HfxZr1-xO2 by Electric Field Cycling for DRAM Cell Capacitor Applications Kim, Seongho; Lee, Seung Hwan; Kim, Min Ju; Hwang, Wan Sik; Jin, Hyun Soo; Cho, Byung Jin, IEEE ELECTRON DEVICE LETTERS, v.42, no.4, pp.517 - 520, 2021-04 |
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