Browse "School of Electrical Engineering(전기및전자공학부)" by Subject NM
Showing results 1 to 16 of 16
| A Broad-Band Achromatic Polarization-Insensitive In-Plane Lens with High Focusing Efficiency Atalay, Ipek Anil; Yilmaz, Yusuf Abdulaziz; Savas, Firat Cem; Kurt, Hamza, ACS PHOTONICS, v.8, no.8, pp.2481 - 2488, 2021-08 |
| A spacer patterning technology for nanoscale CMOS Choi, Yang-Kyu; King, TJ; Hu, CM, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.49, no.3, pp.436 - 441, 2002-03 |
| A Vertically Integrated Junctionless Nanowire Transistor Lee, Byung-Hyun; Hur, Jae; Kang, Min-Ho; Bang, Tewook; Ahn, Dae-Chul; Lee, Dongil; Kim, Kwang-Hee; et al, NANO LETTERS, v.16, no.3, pp.1840 - 1847, 2016-03 |
| An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs Huh, In; Park, Sangchun; Shin, Mincheol; Choi, Woo Young, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.8, pp.3502 - 3507, 2017-08 |
| Doping-Free Nanoscale Complementary Carbon-Nanotube Field-Effect Transistors with DNA-Templated Molecular Lithography Kim, KH; Kim, JH; Huang, XJ; Yoo, SM; Lee, SangYup; Choi, Yang-Kyu, SMALL, v.4, no.11, pp.1959 - 1963, 2008-11 |
| Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs Jeong, Jaeyong; Geum, Dae-Myeong; Kim, SangHyeon, ELECTRONICS, v.11, no.19, 2022-10 |
| High-k HfxZr1-xO2 Ferroelectric Insulator by Utilizing High Pressure Anneal Das, Dipjyoti; Jeon, Sanghun, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.67, no.6, pp.2489 - 2494, 2020-06 |
| Model Analysis of Ridge and Rib Types of Silicon Waveguides With Void Compositions Eti, Neslihan; Kurt, Hamza, IEEE JOURNAL OF QUANTUM ELECTRONICS, v.52, no.10, 2016-06 |
| Novel Approach to High kappa (similar to 59) and Low EOT (similar to 3.8 angstrom) near the Morphotrophic Phase Boundary with AFE/FE (ZrO2/HZO) Bilayer Heterostructures and High-Pressure Annealing Gaddam, Venkateswarlu; Kim, Giuk; Kim, Taeho; Jung, Minhyun; Kim, Chaeheon; Jeon, Sanghun, ACS APPLIED MATERIALS & INTERFACES, v.14, no.38, pp.43463 - 43473, 2022-09 |
| Schottky Tunneling Effects in a Tunnel FET Hur, Jae; Jeong, Woo Jin; Shin, Mincheol; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.12, pp.5223 - 5229, 2017-12 |
| Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors Choi, Sung-Jin; Moon, Dong-Il; Kim, Sung-Ho; Duarte, Juan P.; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.32, no.2, pp.125 - 127, 2011-02 |
| Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era Choi, Yang-Kyu; King, TJ; Hu, CM, SOLID-STATE ELECTRONICS, v.46, no.10, pp.1595 - 1601, 2002-10 |
| Surface plasmon-assisted nano-lithography with a perfect contact aluminum mask of a hexagonal dot array Kim, Eun Sung; Kim, Yong Min; Choi, Kyung Cheol, PLASMONICS, v.11, no.5, pp.1337 - 1342, 2016-10 |
| The Effect of the Ratio of Lines to Spaces for Nanolithography Using Surface Plasmons Kim, Eun Sung; Choi, Kyung Cheol, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.13, no.2, pp.203 - 207, 2014-03 |
| Vertically Integrated Multiple Nanowire Field Effect Transistor Lee, Byung Hyun; Kang, Min Ho; Ahn, Dae Chul; Park, Jun Young; Bang, Tewook; Jeon, Seung Bae; Hur, Jae; et al, NANO LETTERS, v.15, no.12, pp.8056 - 8061, 2015-12 |
| Vertically Integrated Nanowire-Based Unified Memory Lee, Byung-Hyun; Ahn, Dae-Chul; Kang, Min-Ho; Jeon, Seung-Bae; Choi, Yang-Kyu, NANO LETTERS, v.16, no.9, pp.5909 - 5916, 2016-09 |
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