Showing results 6 to 9 of 9
Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping = 플립플랍 비대칭화와 테크놀로지 매핑을 통한 순차회로의 누설전류 감소link Heo, Se-Wan; 허세완; et al, 한국과학기술원, 2007 |
Minimizing leakage power in sequential circuits by using mixed $V_t$ Flip-Flops = 혼합 문턱전압 플립플랍을 이용한 순차 회로의 누설 전류 감소 기법link Kim, Jae-Hyun; 김재현; et al, 한국과학기술원, 2008 |
Semicustom design methodology of power gated circuits for low leakage applications Kim, HO; Shin, Youngsoo, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.54, no.6, pp.512 - 516, 2007-06 |
Supply switching with ground collapse: Simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits Shin, Youngsoo; Heo, Sewan; Kim, Hyung-Ock; Choi, Jung Yun, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.15, no.7, pp.758 - 766, 2007-07 |
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