Showing results 1 to 60 of 127
8-Pipeline-Stage 32-bit Embedded Processor Using Dual Clock Domain Song, Jinook; Lee, Youngjoo; Kim, Bongjin; Park, In-Cheol, IEEE International SoC Design Conference (ISOCC 2011) Chip Design Contest, IEEE, 2011-11-17 |
8051 호환 마이크로컨트롤러의 설계 이용석; 이성원; 강형주; 김진석; 박인철, 대한전자공학회 추계종합학술대회, v.32, no.2, pp.173 - 176, 대한전자공학회, 2000-11-25 |
A 2048-Point FFT Processor Based on Twiddle Factor Table Reduction Kim , JH; Park, In-Cheol, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips 2007), pp.351 - 364, IEEE, 2007-04 |
A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications Woo, R.; Cho,i S.; Sohn, J.-H.; Song, S.-J.; Bae, Y.-D.; Yoon, C.-W.; Nam, B.-G.; et al, 2003 Digest of Technical Papers, 2003-02-09 |
A 32-bit Multithreaded RISC for Embedded Real-time Application 배영돈; 박인철, 한국반도체학술대회 (KSC), pp.249 - 250, 2002-02 |
A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors Bae, Y.-D.; Park, In-Cheol, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC, pp.583 - 586, 2004-10-03 |
A 6Gbps SSD Controller using Low-complexity and Time-interleaved BCH Encoder/Decoder Lee, Youngjoo; Yoo, Hoyoung; Yoo, Injae; Park, In-Cheol, IEEE International SoC Design Conference (ISOCC 2011) Chip Design Contest, IEEE, 2011-11-17 |
A 80/20MHz 160mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications Yoon, C.-W.; Woo, R.; Kook, J.; Lee, S.-J.; Lee, K.; Bae, Y.-D.; Park, In-Cheol; et al, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.142 - 143441, 2001-02-05 |
A Compiled-code Simulator with Reduced Edge Evaluation Yang, W.S.; Park, In-Cheol; Kyung, Chong-Min, APCHDL'98, pp.107 - 110, 1998-07 |
A Fast Reed-Solomon Product-Code Decoder Without Redundant Computations Park, In-Cheol; Lee, HY, 2003 SoC Design Conference(SDC), pp.829 - 832, 2003-11-05 |
A Fast Sine/Cosine Generator with Pipelined CORDIC and Table Lookup Method Shin, M.C.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.281 - 284, 1998-10 |
A Fault-Tolerant Architecture of Embedded Processors for Electric Vehicle Systems 공병용; 김봉진; 송진욱; 유인재; 박인철, 대한전자공학회 추계학술대회, 대한전자공학회, 2011-11-26 |
A Fixed-Point MPEG Audio Processor for Low Frequency Operation Yi, YS; Park, In-Cheol, International Symposium on Circuits and Systems (ISCAS), pp.300 - 303, 2002-05-26 |
A Fully-intergrated reader system for Mobile UHF RFID 이영주; 김태환; 박강우; 임고은; 박인철, 제 17회 한국반도체학술대회, 2010-02 |
A Graph Matching Algorithm for Circuit Partitioning and Placement in Rectilinear Region and Nonplanar Surface Park, In-Cheol; Kyung, Chong-Min, Joint Technical Conference on Circuits/Systems, Computers and Communications, pp.182 - 186, 대한전자공학회, 1988 |
A Hardware Accelerator for Phong Illumination Model in 3-Dimentional Grahpics Kwon, Y.S.; Park, In-Cheol; Kyung, Chong-Min, HUMANTECH, pp.277 - 285, 1999 |
A Hardware Accelerator for the Specular Intensity of Phong Illumination Model in 3-Dimensional Kwon, Y. S.; Park, In-Cheol; Kyung, Chong-Min, ASP-DAC'2000, pp.559 - 564, 2000-01 |
A High-Speed and Low-Latency Reed-solomon Decoder Based on a Dual-Line Structure Kang, HJ; Park, In-Cheol, International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.3180 - 3183, 2002-05-13 |
A High-Speed and Low-Latency Reed-Solomon Decoder Based on a Dual-Line Structure 강형주; In-Cheol Park, 한국반도체학술대회(KCS), pp.233 - 234, 2002-02 |
A Low-Power Variable Length Decoder Based on Successive Decoding of Short Codewords Lee, SW; Park, In-Cheol, CAD 및 VLSI 설계연구회 학술발표대회, pp.157 - 162, 대한전자공학회, 2000-05 |
A LOW-POWERr VARIABLE LENGHT DECODER BASED ON SUCCESSIVE DECODING OF SHOFT CODEWORDS Lee, SW; Park, In-Cheol, International Symphosium on Circuits and Systems(ISCS), pp.582 - 585, IEEE, 2001-05 |
A Methodology for Compatible Microprocessor Design 박인철; 성광수; 홍세경; 공배선; 이승종; 최훈; 경종민, 대한전자공학회 추계종합학술대회, v.19, no.2, pp.993 - 996, 대한전자공학회, 1996 |
A Multi-Threading MPEG Processor with Variable Issue Modes Yang, W.S.; Kim, H.S.; Park, In-Cheol; Shin, M.C.; Kyung, Chong-Min, International Conference on VLSI and CAD(ICVC'99), pp.545 - 548, 1999-10 |
A novel trace-pipelined binary arithmetic coder architecture for JPEG2000 Rhu, M.; Park, In-Cheol, 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009, pp.243 - 248, 2009-10-07 |
A programmable turbo decoder for multiple 3G wireless standards Shin, M.-C.; Park, In-Cheol, IEEE International Solid-State Circuits Conference(ISSCC 2003), 2003-02-09 |
A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, ICCD'99(International Conference on Computer Design), pp.243 - 248, 1999-10 |
A Reverse Caculation for Low Power MAX-Log-MAP Turbo Decoder Choi, HM; Park, In-Cheol, The 12th Korean Conference on Semiconductors, pp.27 - 28, 2005-02 |
A scalable and programmable sound synthesizer Kim, T.-H.; Lee, Y.-J.; Park, In-Cheol, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, pp.1855 - 1858, IEEE, 2009-05-24 |
A single-chip programmable platform based on a multithreaded processor and configurable logic clusters Bae, Y.-D.; Park, S.-I.; Yi, Y.; Park, In-Cheol, 2002 IEEE International Solid-State Circuits Conference, v.1, pp.336 - 337, 2002-02-03 |
A unified parallel radix-4 turbo decoder for Mobile WiMAX and 3GPP-LTE Kim, J.-H.; Park, In-Cheol, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, pp.487 - 490, 2009-09-13 |
ACCENT : A CISC-Type Configurable Processor Core Chang, Y.S.; Park, B.I.; Yang, W.S.; Oh, H.S.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.195 - 198, 1998-10 |
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking Park, In-Cheol; Shin, MC; Kang , SH, IDEC Conference 2002 Summer, pp.119 - 122, 2002 |
An Efficient Approach to Functional Verification of Complex Processors Lee, S.J.; Won, N.R.; Cho, H.C.; Park, B.I.; Chang, Y.S.; Park, S.I.; Park, In-Cheol; et al, International Conference on Chip Technology, 1998-04 |
An Efficient Binding Algorithm for Data-Path Synthesis 박인철, IEEE Korea Section Student Paper Contest, pp.1 - 15, 1991 |
An Efficient Scheduling Algorithm for High-Level Synthesis 박인철; 경종민, The First Semiconductor Workshop for Young Engineers, pp.59 - 62, 1991 |
An O(n3logn)-heuristic for microcode bit optimization Hong, SK; Park, In-Cheol; Kyung, CM, 1990 IEEE International Conference on Computer-Aided Design - ICCAD-90, pp.180 - 183, 1990-11-11 |
Analysis of Optimal Fault-Tolerant Adder Schemes for Wide Bit-Width Processors 공병용; 박인철, 대한전자공학회 하계종합학술대회, 대한전자공학회, 2012-06-29 |
Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000 Rhu, M.; Park, In-Cheol, 2009 IEEE International Conference on Image Processing, ICIP 2009, pp.2665 - 2668, 2009-11-07 |
Area-Efficient Architecture for Joint Estimation of Fine Timing and Interger Carrier Frequency Offsets 김태환; 박인철, The 14th Korean Conference on Semiconductors (KCS 2007), 2007 |
Area-Efficient Digital Baseband Module for Bluetooth Wireless Communications Park, In-Cheol; Shin, MCl; Park, SI; Lee, SW; Kang, SH, 한국반도체학술대회 (KCS), pp.441 - 442, 2002-02 |
Area-efficient memory-based architecture for FFT processing Moon, S.-C.; Park, In-Cheol, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.5, 2003-05-25 |
ARM 프로세서용 부동 소수점 보조 프로세서 개발 김태민; 신명철; 박인철, 대한전자공학회 정기총회 및 추계종합학술대회 , pp.232 - 235, 대한전자공학회, 1999 |
ARM7 호환 32비트 RISC 프로세서의 설계 및 검증 배영돈; 서보익; 이용석; 박인철, 대한전자공학회 추계종합학술대회, pp.416 - 420, 대한전자공학회, 1999 |
Bluetooth 기저대역 모듈을 위한 USB 인터페이스의 설계 Park , SI; Park, In-Cheol, 한국반도체학술대회 (KCS), pp.255 - 256, 2002-02 |
C-Based Design Methodology 박인철, 대한전자공학회 CAD 및 VLSI 설계 연구회 학술발표회, pp.993 - 996, 대한전자공학회, 1997 |
C-based RTL design verification methodology for complex microprocessor Yim, JS; Hwang, YH; Park, CJ; Choi, H; Yang, WS; Oh, HS; Park, In-Cheol; et al, Proceedings of the 1997 34th Design Automation Conference, pp.83 - 88, 1997-06-09 |
Circuit Placement in Rectilinear Region Using Simulated Annealing and Self-Organization Park, In-Cheol; Kyung, Chong-Min, 1988 International Computer Symposium, 1988-12 |
Circuit Placement Using CCP and Simulated Annealing 박인철; 경종민, Conference on Semiconductors, Materials, Components and CAD, pp.215 - 218, 1988 |
Code Generation for Embedded Processors with Complex Instructions Lee, J.Y.; Yoon, H.D.; Park, In-Cheol; Yang, J.H.; Kyung, Chong-Min, International Conference on VLSI and CAD(ICVC'99), pp.525 - 528, 1999-10 |
Coherence Management Unit Saving Modified Lines Internally for Multicore System 김은찬; 김봉진; 김태환; 박인철, 대한전자공학회 하계종합학술대회, 대한전자공학회, 2010-06-17 |
Combined image signal processing for CMOS image sensors Kim, O.; Park, In-Cheol, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.3185 - 3188, IEEE, 2006-05-21 |
Computation-Efficient Image Signal Processing for CMOS Image Sensors KS , K; Bae, EJ; Lee, S; Song , J; Park, In-Cheol, Internationl SoC Design Conference, pp.411 - 414, Internationl SoC Design Conference, 2007-10 |
Customization of a CISC processor core for low-power applications Chang, Y.S.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, ICCD'99(International Conference on Computer Design), pp.152 - 157, 1999-10 |
Design of Efficient Embedded System Lee, YJ; Song, J; Kim, BJ; Kim, E; Lim, G; Park, In-Cheol, IEEE International SoC Design Conference (ISOCC 2010) Chip Design Contest, IEEE, 2010-11 |
Design Rule Check for Integrated Circuit Using PC Park, In-Cheol; Eo, K.S.; Kyung, Chong-Min, KITE Electronics Eng. Symposium, pp.1547 - 1550, 1987 |
Design verification of complex microprocessors Yim, J; Park, C; Yang, W; Oh, H; Choi, H; Lee, S; Won, N; et al, Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems, pp.441 - 448, 1996-11-18 |
DIVA:Dual-Issue VLIW Architecture with Media Instructions for Image Processing Nam, S.J.; Kwon, Y.S.; Park, In-Cheol; Kyung, Chong-Min, 대한전자공학회 CAD 및 VLSI 설계연구회 학술발표회, pp.117 - 122, 대한전자공학회, 1999 |
Early in-system verification of behavioral chip models Park, C.J.; Lee, S.J.; Park, B.I.; Choi, H.; Lee, J.G.; Kim, Y.I.; Park, In-Cheol; et al, High-level Design Validation and Test Workshop 1999, pp.61 - 65, 1999-09 |
Energy-efficient double-binary tail-biting turbo decoder based on border metric encoding Kim, J.-H.; Park, In-Cheol, IEEE International Symposium on Circuits and Systems, ISCAS 2007, pp.1325 - 1328, 2007-05-27 |
Exploiting Intellectural Properities in ASIP Designs for Embedded DSP Software Choi, H.; Yi, J.H.; Lee, J.Y.; Park, In-Cheol; Kyung, Chong-Min, The 36th Design Automation Conference(DAC), pp.939 - 944, 1999-06 |
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