Scaling the Performance of Network Intrusion with Many-core Processors

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In this work, we present a highly scalable network intrusion detection system on many-core processors. To maximize the NIDS performance, we take advantage of the underlying hardware and adhere to four design principles: shared-nothing architecture, computation offoading, lightweight data structure, and flow offoading. Through the experimental results, we find that our design choices can significantly improve the NIDS performance (79 Gbps with 1514B synthetic packets). We believe that our design decisions can be easily extended to other many-core processors and programmable NICs.
Publisher
ACM SIGARCH/SIGCOMM and IEEE Computer Society TCCA
Issue Date
2015-05-07
Language
English
Citation

ACM/IEEE Symposium on Architectures for Networking and Communications Systems, pp.191 - 192

URI
http://hdl.handle.net/10203/199411
Appears in Collection
EE-Conference Papers(학술회의논문)

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