Multiple Clone Row DRAM: A Low Latency and Area Optimizded DRAM
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, Jungwhan | ko |
| dc.contributor.author | Shin, wongyu | ko |
| dc.contributor.author | Jang, Jaemin | ko |
| dc.contributor.author | Suh, Jinwoong | ko |
| dc.contributor.author | Kwon, Yongkee | ko |
| dc.contributor.author | Moon, Youngsuk | ko |
| dc.contributor.author | Kim, Lee-Sup | ko |
| dc.date.accessioned | 2015-06-25T07:02:54Z | - |
| dc.date.available | 2015-06-25T07:02:54Z | - |
| dc.date.created | 2015-06-09 | - |
| dc.date.created | 2015-06-09 | - |
| dc.date.issued | 2015-06-15 | - |
| dc.identifier.citation | 2015 ACM/IEEE International Symposium on Computer Architecture | - |
| dc.identifier.uri | http://hdl.handle.net/10203/199221 | - |
| dc.language | English | - |
| dc.publisher | ACM SIGGRAPH and IEEE TCCA | - |
| dc.title | Multiple Clone Row DRAM: A Low Latency and Area Optimizded DRAM | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | 2015 ACM/IEEE International Symposium on Computer Architecture | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | Oregon Convention Center, Portland, OR | - |
| dc.contributor.localauthor | Kim, Lee-Sup | - |
| dc.contributor.nonIdAuthor | Choi, Jungwhan | - |
| dc.contributor.nonIdAuthor | Shin, wongyu | - |
| dc.contributor.nonIdAuthor | Jang, Jaemin | - |
| dc.contributor.nonIdAuthor | Suh, Jinwoong | - |
| dc.contributor.nonIdAuthor | Kwon, Yongkee | - |
| dc.contributor.nonIdAuthor | Moon, Youngsuk | - |
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