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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

A 5GHz-95dBc-Reference-Spur 9.5mW Digital Fractional-N PLL Using Reference-Multiplied Time-to-Digital Converter and Reference-Spur Cancellation in 65nm CMOS

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dc.contributor.authorKim, Hyo Junko
dc.contributor.authorSang, Jinwooko
dc.contributor.authorKim, Hyunikko
dc.contributor.authorJo, Youngwooko
dc.contributor.authorKim,Taeikko
dc.contributor.authorPark, Hojinko
dc.contributor.authorCho, Seong-Hwanko
dc.date.accessioned2015-05-15T08:26:12Z-
dc.date.available2015-05-15T08:26:12Z-
dc.date.created2015-05-14-
dc.date.created2015-05-14-
dc.date.created2015-05-14-
dc.date.issued2015-02-24-
dc.identifier.citation2015 IEEE International Solid-State Circuits Conference-
dc.identifier.urihttp://hdl.handle.net/10203/198473-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleA 5GHz-95dBc-Reference-Spur 9.5mW Digital Fractional-N PLL Using Reference-Multiplied Time-to-Digital Converter and Reference-Spur Cancellation in 65nm CMOS-
dc.typeConference-
dc.identifier.wosid000355252700106-
dc.identifier.scopusid2-s2.0-84940773709-
dc.type.rimsCONF-
dc.citation.publicationname2015 IEEE International Solid-State Circuits Conference-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationSan Francisco Marriott-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorCho, Seong-Hwan-
dc.contributor.nonIdAuthorSang, Jinwoo-
dc.contributor.nonIdAuthorKim, Hyunik-
dc.contributor.nonIdAuthorKim,Taeik-
dc.contributor.nonIdAuthorPark, Hojin-
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