Inability to scale down the threshold voltage of CMOS transistors due to sub-threshold leakage concerns, coupled with continuous dimension scaling has aggravated dynamic power density of modern microprocessors.The resulting heat density limits the operating frequency of microprocessors, giving room to dynamic voltage and frequency scaling (DVFS).DVFS is effective in reducing both the dynamic and leakage power consumption, preemptively when temperature rises beyond limits, and opportunistically to save energy when microprocessors are lightly loaded.
When applied to on-chip cache memories, however, voltage scaling is limited to a minimum voltage, called VCCMIN.Scaling the supply voltage below VCCMIN surpasses the noise margins of many SRAM cells, rendering them unreliable. This problem owes to inherent artifacts or nanoscale fabrication, known as process variations. Thus, process variations either limit reliability or low power operation.
To ensure reliable cache operation below VCCMIN, a fault tolerant mechanism is inevitable. This dissertation reviews such fault-tolerant caches design which exploit various within-cache and extra-cache redundancies. It then presents two novel techniques, fault buffers and Macho, which provide variation-resilience in small L1 caches and larger L2 caches, respectively. Fault buffers belong to the class of extra-cache redundancies which substitute for faulty words only, in a word-accessed L1 cache. A fully-associative design of fault buffers minimizes area overhead, a banked-approach limits latency and access energies while a DVFS-controlled power-gating infrastructure curtails leakage power by disabling underused banks.
The second technique, Macho, emulates a trade-off between cache capacity and low-power by presenting a within-cache word substitution technique. "Macho" stands for a "Model-oriented and Adaptive Cache Organization". One of the main contribution is the development of a rigorous closed-form reliability model of word...