Memory scheduling techniques for multi-core secure processors

Abstract

The people who use commodity computer system worry about the security of their data. Architecture support for security can protect against software attacks, but we should protect against hardware attacks also. To protect against hardware attacks, the secure processors architecture which uses encryption and authentication can be employed. However, secure processors require some components such as counter, hash tree node, and MAC to guarantee the integrity of data and hide data against malicious users. These components make memory bandwidth congested. Prior secure processors schemes were proposed in single-core processors environment. In the single-core secure processors, the effect of these components on memory bandwidth is not noticeable. However, the impact of the overhead of memory bandwidth causes significant performance degradation in multi-core secure processors. In this study, we propose two simple memory scheduling algorithms and reduce the performance degradation of secure processors architecture in multi-core processors using the modified memory scheduling algorithms. We propose and evaluate two simple memory scheduling algorithms. First, we assign priority to the components in critical path. Second, we try to exploit Bank Level Parallelism(BLP). Our simulation result is on McSimA+ with Gems ruby memory modules using SPEC CPU 2006 benchmarks. Our memory scheduling algorithms improve the performance of multi-core secure processors to average 8% in relaxed mode and average 3% in strict mode.